Research And Design Of Digital Filter In Sigma-Delta ADC

With biomedical,HiFi audio and smart instruments and other areas of the growing demand for signal acquisition accuracy,Sigma-Delta ADC as a high-precision analog-to-digital converter,has been widely used.It is composed of two parts:analog modulator and digital filter.The analog modulator mainly uses oversampling and noise shaping techniques to move the in-band noise out of the bandwidth,thereby achieving a high signal-to-noise ratio.The digital filter is mainly responsible for filtering the noise outside the signal bandwidth,and down sampling the modulated signal to reduce the amount of data storage,and the workload of the post-stage circuit for data processing.The way to improve the accuracy of Sigma-Delta ADC can be achieved mainly by increasing the oversampling rate and increasing the modulator order.But this will increase the design difficulty of analog modulator,and put forward higher requirements for the design of digital filter.This is because the digital filter often occupies the main area and power consumption of the chip.It not only needs to implement the good performance of the filter,but also needs to consider the oversampling rate and the accuracy requirements on the area and power consumption.This paper analyzes the overall structure of the digital filter suitable for high decimation factors based on the working principle of Sigma-Delta ADC and digital filter.By analyzing the recursive structure and the non-recursive structure of the CIC filter,a combination of the two is used to optimize power consumption and area.For the problems of the passband attenuation and folding band aliasing of the CIC filter,a compensation filter based on sine compensation and increasing the zero points is used to compensate.As a result,the attenuation of the passband decreases from 1dB to about 0.05dB,and the attenuation of the folded band decreases from-99dB to-142dB,achieving better passband compensation and aliasing suppression.In terms of hardware implementation,by combining the compensation filter with the CIC filter and using poly-phase structure,the power consumption is reduced.Considering the characteristic that the half-band filter coefficients are symmetrical and nearly half is zero,this paper adopts a half-band filter as the last stage,and introduces CSD coding and time division multiplexing of the multiplier.The proposed digital filter is simulated by Simulink and implemented by RTL code.Through spectrum analysis,the filter performs well and achieves 512 times downsampling.The output of the analog modulator with an in-band signal-to-noise ratio of 113.4dB is filtered out of the noise by the digital filter and the signal-to-noise distortion ratio still reaches 109.9dB.The effective number of bits is up to 18 bits.Finally this paper completes the layout design for the proposed digital filter,using TSMC 0.18?m CMOS technology.The area of the filter is about 0.152mm~2.