Research On The Crucial Technologies Of Frequency Hopping System Based On Cognition

Frequency-Hopping Spread Spectrum(FHSS)is a technique that can avoid external interference by changing the transmitting frequency constantly.It has excellent anti-interference and anti-fading performance.With the improvement of its performance,the technologiesof frequency synchronization are also getting more and more difficult.Therefore,how to obtain more accurate and fast frequency synchronization is one of the key problems to improve the performance of frequency hopping system.One of the common factors that affect the synchronization performance is that the frequency of communication is polluted,which leads to the increase of acquisition decision error.An effective means to solve this problem is the cognitive radio technology.The two sides of the communication can get free or low utilization frequency points through this technology,and use the common part to carry on information transmission.The premise of this process is that the two sides can find each other,as the rendezvous technology of the channels.In order to improve the performance of frequency hopping communication system,this paper combines the frequency hopping system and cognitive radio to study the physical layer and MAC layer of cognitive-hopping system,and test and verify the hardware-in-the-loop simulation.In order to solve the problem of large amount of data in the simulation verification process,weuse the SATA3.0-based high-speed storage and transmission program,design and implementation of FPGA-based sandwich plate SATA controller,and simulation and test are carried out.The main research contents and contributions are as follows:The working principle of the cognitive frequency hopping system is analyzed,and the frequency-hopping communication part and the intersecting part of the system are modeled.Firstly,the working principle of frequency-hopping system by common radio frequency is analyzed.Then,according to the analysis of its working principle,the block diagram of cognitive frequency hopping system is given,and the cognitive radio workflow.Finally,the key parameters and models used in the simulation of the system are listed.An adaptive thresholding structure in frequency hopping synchronization is improved,and the performance of the three acquisition methods is improved by applying the proposed method to the different acquisition algorithms.Firstly,this paper introduces the working principle of three kinds of frequency hopping synchronization methods: serial capture,parallel capture and waiting search.Then,an adaptive threshold-based method is analyzed,and the shortcomings of this method are pointed out.Finally,the performances of the three methods based on improved thresholds are analyzed and compared with those before the improvement,and the performance of the three methods is compared with single-frequency interference,multi-frequency interference and wide-band interference.The performance of the proposed method is analyzed and compared.Impact.The simulation results show that the improved method can acquire better performance than before.Study the algorithm of cognitive convergence under three kinds of symmetric networks,and compare the performance of the three algorithms in the asynchronous and asynchronous modes under the asymmetric network.Firstly,the principle and performance of MC algorithm,GOS algorithm and optimal AQCH algorithm are expounded briefly.Then,the assumptions and parameters of cognitive network environment are given.The three algorithms are applied in asymmetric network,The simulation results show that the performance of the three algorithms is better than that of the asynchronous and the asynchronous methods.Finally,based on the simulation results,the advantages and disadvantages of the three algorithms in asymmetric networks are discussed.Analyze the SATA3.0 protocol,according to the requirements of system testing,the host controller is designed and board testing.First of all,the protocols of SATA3.0 are analyzed layer by layer,including application layer,transmission layer,link layer and physical layer.Then,according to the requirements of system test,Verilog language is used to design the master controller.Finally,the IP core is tested on the board,and the Chipscope grab signal is used to analyze the function and timing of the IP core.