The Verification And Optimization Design Of Floating-Point Adder Of X-DSP

With the development of integrated circuit,it has been widely used in communication,household appliances,aerospace etc.Consequently,the improvement of optimization design and performance is very important.Floating-point adder determine the performance of microprocessor,so,it is more important to design a floating-point adder with high quality.X-DSP is a high-performance 64-bits multi-core processor,with 8 core,each of them has several floating-point adders.This paper research of design,optimization floating-point adder in the core of X-DSP,this paper has accomplish the work as below :1.This paper present the background and significant of optimization design of floating-point adder,analysis the critical path and algorithm of two-path floating-point adder.2.In the logic block for absolute value of exponential difference less than 1 of two-path floating-point adder,the leading 1 predection take place of leading 1detection,then the leading 1 detection has changed from serial to parallel with adder.Therefore reduce the critical path delay for two-path floating-point adder,improve the speed of operation of two-path floating-point adder.3.Deeply verification for the two-path floating-point adder,and then,synthesize the optimized two-path floating-point adder.Experimental data show that,the optimized two-path floating-point adder than before optimization critical path delay is reduced21%,area has increased 70%,power has increased 23%.