Research On Floating Point Multiply Add Unit Of High Performance Microprocessor

Floating point operations,floating point multiplication and floating point addition are the two typical operations that use the highest frequency.The floating point multiplication and addition unit(FMA)is able to complete the obvious advantage of floating point multiplication and addition operation at the same time,so that the performance of the computer floating point calculation can be significantly improved.However,for the single floating point multiplication and floating point addition,the floating point fusion multiplier increases its operation delay,which has an effect on the performance.Therefore,it has important practical significance to study the floating point multiplier adder and the separate floating point multiplier.In this paper,the design and implementation of high performance floating point fusion multiplier and separated floating point multiplier are designed,and the optimization techniques are studied.The advantages and disadvantages of two kinds of floating point multiply add parts are analyzed,and the high performance floating point multiplication unit is designed for high performance computing.Through to high performance microprocessor floating point multiply add unit of a more comprehensive and in-depth research,and to the two structure components to be implemented and validated by comparison,this paper research content mainly includes the following several points:1)In-depth study of the overall structure of floating point multiply add components and the key components of the structure and related implementation techniques,including the floating point multiplication plus structure and the separation of floating point multiply add structure.2)The design and implementation of the floating point multiplication and addition structure using 7 levels of the whole water,and study the structure of the floating point fusion multiplier and the sub modules to complete the RTL level modeling and simulation verification of the whole component.Can achieve single / double precision floating-point multiply add,floating-point addition / subtraction,floating point multiplication and other operations.For the LZD algorithm were studied,using monotone(monotonic string)string conversion of leading zero detection algorithm based on and improve the parallelism.3)With carry modified the structure of array multiplication;for floating-point fused multiply add structure in the main adder design using based on EAC structure to be realized,reduce the floating-point fused multiply add components of FMA logic series,improve the execution speed.4)The overall structure of the separated floating point multiply add unit is analyzed,and the "4+4" class flow structure is adopted to realize the floating point multiplication and floating point addition.Complete the RTL level modeling and simulation verification for the whole separated floating point multiply add unit.The channel separation of floating point multiplication and floating point addition is realized.5)Separation fused floating point passenger structure,adding part with double channel was designed and implemented.The points for NPath and fpath two pathways,the critical path in order to shift or normalized shift only need a reduced a shifter delay.The order of addend shifter down to the multiplier and multiplier,no longer parallel execution.To sum up,this paper is based on the important influence of floating point multiplication and floating point addition on the performance of the operation,the floating point fusion multiplier and the separation of floating point multiply add parts are studied and compared.For,with a smaller area of floating-point fusion can realize floating-point multiply add operation multiply add unit,but for a single floating-point addition and multiplication delay,need to take 7.The separation of MAF area increased but for a single floating-point addition and floating-point multiplier rule requires only 4 beat delay is small.