Design And Optimization Of1GHz64-bit High Performance Floating-point Adder

Floating-Point Adder is an important part of high performance FPU(Floating PointUnit), its performance influences FPU processing capacity. For the need of theinnovative high performance DSP, research on fast floating-point addition/subtractionalgorithm structure is made, and the logic design and optimazation of a64-bit highperformance floating-point adder is completed in this thesis.Related research achievements of floating-point adder are investigated in this paper.What’s more, a deep comparision of Single-Path, Two-Path and Triple-Path floating-point adder, etc. several algorithm structures is made. According to the X-DSP FPUoperation requirements, the overall structure of64-bit high performance floating-pointadder is put forward, which uses Combined Rounding Two-Path floating-point adderand balances3-level pipiline.In order to attain the goal of the1GHz frequency, the key sub-modules of floating-point adder are optimized at algorithm level, which involves three main modules andseveral optimized points. Taking consideration of the structure characteristics of Two-Path floating-point adder and accessibility of1GHz frequency, the logic structure ofCombined Rounding algorithm is optimized. Besides,54-bit compound adder is imple-mented by adopting parallel prefix algorithm in order to improve the operation speed.What’s more, the parallel execution is adopted, that is,54-bit compound adder is reaso-nably split into two compound adders to reduce the key path delay. Finally normaliz-ation shift is implemented using leading-one prediction architecture with serial correct-ion, which achieves good balance between area and delay.This thesis synthesis the design by logic synthesis tool, evaluates timing, and opti-mizes the RTL code according to the synthesize results. Using the techniques of balanc-ing pipeline, logic replication and shannon extended operation, can greatly reduce thecritical path delay. The result shows that the logic delay of optimized adder is not morethan700ps in45nm standard process, and that30%margin of timing is reserved forphysical design to obtain1GHz frequency.In order to verify logic function of the design, various verification methods areused in this thesis. The basic function of the design has been verified comprehensivelyby means of directed testing method. Besides, exhaustive testing methods is used toverify the boundary conditions of the operands and the algorithm structure. What’s more,function coverage verification of adder is accomplished by coverage-driven randomtesting method, and complete benchmarks with constraits are generated. And assertion-based verification is used to improve verification efficiency. Finally, a common stimuluslibrary of mathematical-functions is established for function verification. Through themulti-level verificaton, the correctness of floating-point adder can be insured.