Research And Design Of High-pergormence Floating-point Adder

With the increasing accuracy of data, floating-point unit becomes more and more important inmodern microprocessor. According to the relevant reports, floating-point add operations accountedfor more than55%of floating-point operations. Therefore, the floating point adder is the mostfrequently used part in floating point unit (FPU). Floating point adder is one of the most importantparts of modern microprocessors and digital signal processing. The IEEE-754definitionof floating-point number is very complex. So the hardware implementation of floating-point adder isslow.This paper discussed two-path algorithm and the improved structure of two-path algorithm basedon the structure of traditional floating point adder. In the two-path structure, analysised the leading1(leading0) prediction algorithm, the barrel shifter and some other key structures. After researchingthese key modules, decided to use the two-path algorithm as the structure of the floating-point adder.In the leading1prediction module, used the pre-coded logic in the LOP algorithm, and then detectedthe leading1of the pre-coded logic signal. Moreover, barrel shifter is used to avoid the time-delay.Mantissa adder as an integral module restricts the performance of floating point adder. This paperproposed an advanced design based on parallel-prefix Ling adder. In order to further improve the Lingadder’s performance, the preprocessing block and carry propagation block are all optimized to reducethe delay path for sum generation. Experimental results indicate that the32-bit proposed adder has animprovement of18percent time delay and20percent area compared to the32-bit traditional Lingadders. In the design of floating-point adder, a24-bit proposed adder is used in the mantissa addermudule.This paper completed a series work of the design of floating point adder: architecture selection,algorithm research, code writing, simulation and physical synthesis. All the programs used VerilogHDL. All the data were obtained by the Synopsys DC synthesis. Experimental results showed thatthe design of the floating point adder achieved the expected targets.