Designing High-Performance Floating-Point Adder

Floating-point Unit is a special microprocessor circuitry unit that deals with floating-point arithmetic operations, which is widely used in Scientific Arithmetic, CPU, DSP(Digital Signal Processing) and Image Processing,, The thesis discusses how to implement high-performance floating-point processing unit based on the research of its implementation algorithm and its implementation structure. The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure. The main content includes exponent comparator, leading zeros detector and leading zeros anticipatory logic, while leading zeros anticipatory logic is the core. The former two are implemented with logarithmic complexity algorithm. Leading zeros anticipatory logic is implemented based on a set of unified product rule, which can diminish the potential one bit error of original ones. The product rule is very simple and easy to implement, and it doesn't increase additional delay.Based on the implementation algorithm and schematics, a lot of comprehensive experiments are performed, and then the experimental data and conclusions are shown. The data and conclusions prove that these designs are better than the original ones; the floating-point adder is really optimized.