The IP Core Design And Floating-point ALU Research In 32 Bits DSP

Floating point arithmetic is one of the most important one in high performance arithmetic. In order to satisfy the requirement of applications, some of the microprocessor and high performance vision card have the performance to deal with super precision arithmetic. But for the methods of how to realize super precision arithmetic, there is no more information. Based on the work in designing a FALU(floating-point arithmetic logic unit) in the 40 bit floating point DSP, this dissertation gives a systematic research on the every stages of the FALU considering delay, area and complex. Since floating-point algorithmic whose core is floating point adder, will lead to more operations, so it is essential to make full use of floating-point addition of the various functional modules. In order to realize other functions and to achieve timing requirements, the design will be more complex. Based on the study of adder including floating-point adder algorithm, analyzing these kinds structures, we choose the LOP floating-point add as the main assembly of FALU. This FALU could deal with 22 kinds arithmetic and logic operations, all these operations are done in one clock cycle. The fix adder and leading one predetection are in parallel way, this could reduce the data-path delay, make sure the performance of this FALU is fitted with design spec. Character vectors and random vectors are used to test the FALU, the DSP IP core includes this FALU has passed the software and hardware test.The floating-point arithmetic logic unit synthesis with SMIC 0.18um technique, the result show the high performance, under the 1.8V typical condition, the critical path of the multiplier is 6.7ns.