Research On High-efficient Of Polar Codes Hardware Decoder

Polar code has been proved to have better error correction performance than LDPC and Turbo codes.However,the decoding algorithm still has the disadvantages of high-complexity and long latency,making the hardware structure of the decoder complex and low throughput.For the problems of polar code hardware decoders,this paper makes three key contributions:First,a new type of processing element—node interconnection processing element architecture is proposed,which replace the absolute value comparison unit of the F-node by using simple gate-level circuit and reduce the G-node"symbols-complement"conversion and"complement-symbols"conversion circuits;Second,aiming at the characteristics that the upper and lower halves of the hardware decoder are independent,a bit width quantization technique is adopted,and the memory bandwidth is reduced by reducing the size of the internal operation value of the hardware decoder,thereby further reducing the hardware resource consumption;Third,in combine with the pipeline architecture,by inserting registers into the decoder layer,the length of the internal signal connection of the hardware decoder is shortened to reduce the line delay,and the maximum clock frequency that the hardware decoder can support is increased,thereby improving the processing speed and throughput of the decoder;Finally,based on the proposed processing element architecture and optimization techniques,for successive cancellation in polar code decoding algorithm and successive cancellation list algorithm,this paper implements the corresponding hardware decoder on the FPGA,and tests the error correction performance,resource consumption,and maximum frequency of the hardware decoder in detail.Experimental results show that the required hardware resources of the proposed processing element structure are reduced by 30.8%compared with the conventional processing element.Based on the proposed processing element,the hardware resources required for the SC hardware decoder are reduced by 20%when the code length is greater than 2~7 bits and the maximum frequency is increased by 5%.The hardware resources required for the designed SCL hardware decoder are reduced by 20%,and the maximum frequency is increased by 20%.