Research On Polar Code Decoder Based On Belief Propagation Algorithm

Polar code is a channel coding scheme that can be strictly proved to achieve the Shannon limit in memoryless channel.In recent years,it has gained extensive attention from researchers.Polar code has been selected by 3GPP as the control channel coding scheme for 5G enhanced Mobile Broadband scenarios in 2016.To meet the higher-speed and higher-performance commands of 5G,more flexible and high-efficient decoder is required.This paper focuses on the decoding algorithm and hardware architecture of the belief propagation(BP)of polar code.The main work is as follows.1)This paper proposes an alternate-structure scheduling scheme based on BP,which improves the reliability and efficiency of soft messages of node during iterations.Due to the serial nature of updating rules for the conventional BP algorithm,the efficiency of updating soft messages is limited.The updated soft messages in the proposed decoding algorithm can be directly used to update the next-stage node,avoiding the storage of intermediate data in the memory.Based on the analysis of the factor graph,the last-stage processing elements in the factor graph are removed.Meanwhile,the early stopping criterion based on the connected sub-factor graph(CSFG)criterion freezing is improved to accelerate the decoding convergence,and reduce the number of decoding iterations.Based on this,a BP decoder based on alternate-structure scheduling is proposed.Synthesizing on Stratix V 5SGXEA7N2F24C2,the working frequency of the decoder can reach 275MHz.When Eb/N0=4dB,the average decoding latency of the proposed BP decoder is 107ns.Compared with the dual-column BP decoder,it can be reduced by 50.6%.2)A BP decoder compatible with polar code and the low-density parity check(LDPC)code is presented.Based on the analysis of BP decoding algorithm,a compatible processing element for both algorithms is proposed.In order to reduce the resources consumption,a memory architecture compatible with of polar codes and LDPC codes is designed,which can be utilized to store the soft information of the nodes in different standards.Based on this,a BP decoder compatible with polar codes and LDPC codes is proposed and synthesized on 5SGXEA7N2F24C2.The synthesis results show that compatible decoder can be utilized to decode(128,64)polar codes and(2240,1408)LDPC,and the working frequency of the decoder can reach 160MHz,the throughput of LDPC code can reach 178Mbps at 4dB,and the throughput of polar code can reach 318Mbps at 3dB.Meanwhile,the register resources of compatible decoder are only 37%of the total resources,and the cost of logical resource is 14%of the total chip resources,which is lower than that used when the two codewords are decoded separately.