Performance Analysis Of Polar Code And FPGA-Based Implementation On SCL Decoding Algorithm

Since the Shannon theorem was proposed by A.E Shannon,it has been a hot topic in the field of communication to look for the channel coding technologies which can approach Shannon limit.In the past few decades,two Shannon-limit-approaching channel coding technologies Turbo code and LDPC code were getting riper with the wide application in modern communication.Once polar code based on the channel polarization was proposed by a Turkey professor Erdal Arikan,many researchers in the filed of channel coding were greatly attracted.With excellent decoding performance,polar code has linear complexity both in encoding and decoding,which bring it very pratical significance.Based on channel polarization,the thesis is aimed at doing deep research on the characteristics of polar code together with its encoding and decoding methods.Meanwhile,we proposed a FPGA-based design of SCL decoder.The main contents and innovations are listed as follow:(1)Compared with basic rules of polar code,we study the basic coding principles of Turbo code and LDPC code,and present their merits and demerits.By combining and splitting specific channels like BECs and BSCs,we study the generation and properties of channel polarization.Without loss of generality,we can apply the conclusions to other common channels like AWGNs in real communication systems.(2)We study the way that polar code can be construct based on polarization phenomenon,in which sense the generating matrix can be formed in a recursive manner.Then we focus on the decoding algorithms like SC?SCL?CA-SCL?BP,and simulate the decoding performance under different conditions.Channel selecting is a very important part in polar code.On the basis of classical channel selecting methods,we propose a new method.According to the charachteristics of AWGN,first we transform it to BSC channel,and then complete channel selecting using Bhattacharyya parameter of BSC channel.The simulation result shows that the new method outperforms the traditional method.(3)We further study the minimum-sum algorithm which is suitable for hardware implementation and then simulate this algorithm with different quantization width.Having analysized the simulation result,we made the final decision with 8 bits LLR and 12 bits path metric.In the end,we summarize the evolution of the design on SC decoding hardware architechtures.To reduce the consumption of system resources,we propose a single-processing-element architecture based on the traditional semi-parallel architechture,which is applied to the SCL decoder we propose in the thesis.More importantly,we use Verilog language to describe every single module under the top module and introduce detailed function of them.Then we use Modelsim to do the RTL simulation under 300 MHz clock frequency and finally draw the conclusion that the throughput of the decoder can be up to 6.24 Mbps while the hardware utilization is only 6%.