Performance Analysis Of Polar Codes And FPGA-based Implementation On SCS Algorithm Decoder

Considered to be the only one can approach to the channel capacity,polar code has become a hot topic since it was proposed by A.E Shannon in 2007.As the development of the communication technology,polar cods play a vitally important role in modern communication because of its low complexity and good performance,and researching on polar codes is of pratical significance.The thesis focuses on the encoding and decoding method.Based on the analyzation of decoding performance,we proposed a FPGA-based design of SCS decoder.The main contents are as follow.(1)Turbo codes and LDPC codes are widely used in modern conmmunication.We study on these classic iterative decoding-codes and compare them with polar codes,finally show the specific structure and good performance of polar codes.(2)We research on the channel polarization and the encoding and decoding theory.On the encoding,we show how the generating matrix is formed in a recursive manner.Based on the research of classical channel selecting methods,we propose a new selecting method for AWGN channel,that we transform AWGN channel to BSC channel and select channels using Bhattacharyya parameter of BSC channel.The new method is called BSC-Z(W)method in thesis.On the decoding,We focus on the decoding algorithms like SC?SCL?SCS,and simulate for the decoding performance under different conditions.From the simulation,SCL and SCS algorithm perform well.In addition,the BER of SCS algorithm is similar to that of SCL algorithm in the condition of the same searching width,but its complexity is much lower,which shows the pratical value of SCS algorithm.(3)We propose FPGA-based implementation on SCS algorithm decoder.According to the simulation on software,we set adapted paramters;then propose the minimum-sum algorithm and quantization scheme which is reasonable for hardware implementation;propose a single-processingelement architecture for LLR and double-FIFOs-stack architecture;and design feedback module to simplify the computation.After using Verilog HDL to describe modules on Quartus II and simulating on Modelsim under 300 MHz clock frequency,we can draw the conclusion that the decoding throughput can be up to 6.24 Mbps whilet the hardware utilization is only 4%.