Design And Implementation Of Polar Decoder For 5G

Polar code is determined as the control channel coding scheme in the 5th generation mobile communication network(5G)enhanced mobile broadband(eMBB)scenario.Therefore,the polar code is an important supporting technology for future mobile communication systems,and is also the research focus on 5G physical layer technology.The polar code c an use a successive c ancellation(SC)decoding method.The performance of the polar code with SC decoding is not ideal.Long code length polar code has good performance,but it also faces the problem of increased decoding latency.Faced with the requirements of low latency and high throughput in future mobile communication scenarios,the high decoding latency of the polar decoder and the low throughput rate have become a major practical challenge.To achieve this goal,in this paper,we first study and summarize the general sequential logic law s(SLL)of SC decoder.These reflect the timing switch relationship between the operations at various decoding stages.In order to ensure good decoding performance after fixed-point quantization and hardware resource consumption,this paper proposes a hardware quantization scheme based on the minimum mean square error.Then,combined with the decoding principle and structural characteristics of polar code,a new low-latency multi-bit parallel polar SC decoder is is pres ented.It is a novel reformulation for the last two stages of SC decoding so that 4 bits can be de decoded simultaneously,increasing the parallelism degree of decoding and reducing the decoding latency.In addition,to save hardware resource,this approach optimizes the partial-sum storage structure through hardware multiplexing.Finally,a hardware link simulation platform is built,based on Stratix V FPGA board and PC.The performance of the proposed multi-bit polar SC decoder is verified by the actual hardware circuit board.As a result,the proposed multi-bit polar SC decoder can reduce the decoding latency significantly,compared with the traditional SC decoder,with the same performance.In terms of hardware implementation,the waterfall curve of the test performance by FPGA is close to the software fixed-point result.This paper also report and analysis the comparison result of the actual hardware decoding latency and the consumption of hardware resources.The development and verification of polar decoder are accomplished.