Research On SoPC Image Processing System Architecture Based On Nios ? And Hardware Accelerated Core

With the rapid development of computer technology,image processing technology and microelectronic technology,digital image processing technology has been applied to the higher fields of image recognition,computer vision,deep learning and so on.And at the same time,the requirement on the speed and accuracy of digital image processing is also increasing.At present,the general computer is used to process digital images,and the technology is mature.But there are shortcomings such as high cost,large volume,high power consumption and slow speed.ASIC has obvious advantages compared to general computer.But as a fixed integrated circuit,it has a single function,long development cycle and high design cost for ASIC.Digital signal processor(DSP)has some advantages on digital image processing because of its own hardware structure.But the cost of DSP image processing system is high and the peripheral circuit is complex,which makes it difficult to be developed and flexible to be designed.The field programmable gate array(FPGA)has been widely used in the field of digital image processing because of its advantages of high integration,low development cost,strong parallel processing ability and good stability.The time-consuming operation in digital image processing can be designed with the FPGA hardware logic resources.Combining FPGA's parallel processing capability with the flexible development ability of Nios II processor is the key for the implementation of SoPC digital image processing system based on Nios II and hardware accelerated core.With a view to solving the above problem,the architecture of SoPC image processing system based on Nios II and hardware accelerated core has been deeply researched in this paper.The included main contents:(1)The architecture of SoPC image processing system based on Nios II and hardware accelerated core has been proposed.The problems of logic control and data communication between hardware logic acceleration core and Nios II processor has been studied,and two communication schemes based on I/O interface register mapping and Avalon interface logic package has been designed.(2)In the framework of the SoPC digital image processing system,the convolution hardware accelerated core of 3x3 and 5x5 templates is designed respectively using the hardware multiply-accumulator and parallel adder,which has been widely used in image processing.(3)The Sobel edge detection accelerated core based on 3x3 convolution core has been designed,and the image smoothing accelerated core based on 3x3 and 5x5 convolution core has been designed.The SoPC image processing system platform based on Nios II and hardware accelerated core has been built to test the edge detection and image smoothing effect of digital image.The function simulation of convolution acceleration kernel of 3x3 and 5x5 have been carried out in this paper using Modelsim SE,and the results show that the convolution accelerated core is effective for convolution operation.The function simulation of the Sobel edge detection acceleration core has been carried out,and the SoPC digital image processing system designed in this paper has been built on the FPGA digital image development platform.The testing of the Sobel edge acceleration core is carried out by selecting different threshold,and the simulation and test show that it is effective to extract the edge information of the image using Sobel edge detection accelerated core,and it has a better edge detection effect in the case of threshold value of 20.Simulation and test of 3x3 and 5x5 image smoothing accelerated core has been carried out,and it shows that the accelerated core designed is effective in smoothing the image.The effect of image smoothing is more obvious with the increase of smooth convolution core,and the more blurred the image is.