| Generally, the edge feature is an area which contains a lot of information of an image. It has been regarded as the utmost important study by numerous of researchers. The image edge feature detection, based on a particular rules, is a means of detection and extraction in a digital image. The traditional way of image edge feature detection is to use the image processing software on PC to achieve edge detection for static digital image by a certain algorithm. Although this way has certain stability in the process, it cannot meet practical needs from a large extent.This paper is based on the SOPC technology and the principle of image edge feature detection. Building on the modular design of FPGA, we use the Verilog HDL programming language to solidify the Sobel edge feature detection algorithm on the FPGA chip. The image data acquisition of our system is achieved by an external camera, and the test results are displayed on the monitor through the VGA cable. We also embed soft core processor Nios II to speed up the system and to achieve the output control of different test results under different thresholds value. Using this system can have an effective way to achieve real-time image edge feature detection and get rid of the traditional limitations of realizing on PC only, which makes the whole work of image edge detection more flexible. Meanwhile, the realization of this design provides a powerful guarantee for image registration based on SOPC, etc in the future. |