FPGA Implementation Of Image Compression And Reconstruction Based On Compressed Sensing

The railways that are not electrified are in a harsh environment and the resources for calculation,storage,and transmission are scarce.It is very difficult to use the electronic equipment to collect and handle railway image following the traditional Nyquist sampling law.Compressed sensing as a new sampling compression theory,the sampling frequency is no longer limited by the highest frequency of the signal.Compressed sensing makes full use of the sparsity of the signal,and uses the measurement matrix to sample and compress the signal,the high-dimensional signal is reduced dimensionally to obtain a low-dimensional signal.Finally,the original signal can be reconstructed in the low-dimensional signal through a suitable reconstruction algorithm.Nyquist sampling theory compresses after sampling and discards redundant information in the process of compression.Compressed sensing directly reduces the sampling point and completes sampling and compression synchronously,saving a lot of computing,storage,and transmission resources compared to Nyquist sampling compression.Field Programmable Gate Array(FPGA)chips have the advantages of small size,flexible programming,online erasability,low power consumption,hardware parallel operation,fast operation speed and many pins.It also has the ability to implement complex image processing algorithms and is a good platform for image processing.Compressed sensing algorithm has the advantage of greatly reducing sampling data while also ensuring good data recovery with less sampling data.Combining the advantages of compressed sensing theory with the advantages of FPGA chip,using SOPC technology,hardware and software are combined on the FPGA platform to achieve image compression.Compressed sensing theory is used on FPGA platform to compress and reconstruct image with high quality and good real-time performance.The main contents are as follows:First,the principle of compressive sensing algorithm is introduced.The compressed sensing process of the image includes the following steps: firstly sparse the image data;then sampling and compressing the image data with the help of measurement matrix;finally,by using a suitable reconstruction algorithm,the original data can be reconstructed from the small amount of compressed data.Secondly,this paper uses MATLAB software to simulate the three parts of the compressed sensing algorithm: sparse representation,data measurement and image reconstruction.The performance of the algorithm is compared and analyzed.It also provides theoretical support for the implementation of compressed sensing theory in FPGA.Then,using the on-board camera to capture image data as input,image is processed on the FPGA by the compressed sensing algorithm,and the output image is displayed on the liquid crystal display through a video graphics array(VGA)interface.The Verilog HDL(Verilog Hardware Description Language)language is used to design the image acquisition controller module and the image output controller module.The simulation is performed using Modelsim software,and verification is performed with the SignalTap II software to ensure correct module design.Finally,using SOPC technology to build a hardware platform embedded Nios II soft-core processor.The Nios II soft processor is responsible for compressing and reconstructing image data.In the Integrated Development Environment(IDE),a program for compressed sensing processing software is written in C language,and the software program runs on the Nios II soft core processor.This article from the algorithm to the simulation and then to achieve,realizes the application of compressed sensing in image processing engineering combined with hardware and software...