Research On The Bit Of D/A Mixed Signal Based On MTM Bus

As the current rapid progress in the development of integrated circuits,a variety of integration and complexity of mixed-signal circuits increases constant ly.The test circuit becomes more and more difficultly,and some of the traditi onal testing methods cannot fully meet the current testing needs.Therefore,to meet the actual need for the present circumstances,the research of complex an d system-level testing need to be carried out.In this paper,by reviewing of th e relevant literature within recent years,it is summarized that the current test specifications and test methods of mixed-signal boundary-scan technology,and the key techniques and methods for mixed signal boundary scan are studied.A n approach was presented about testing hybrid digital and analog circuits based on the connection of test and maintenance bus.The thesis is to achieve com posite application about boundary scan IEEE1149.1,.4 and.5,and to provide an efficient and feasible build-in-test method.The research contents and results of this paper were as follows:1)Boundary scan standards and their combination rule were researched.C ombined with the four work ways of Build in Test and the three analysis mod es of Boundary Scan Test,the diagnosis methods were researched.After studie d the three standards of IEEE1149.1,.4 and.5,the differences between them were analyzed,and the feasibility about combination application of them was p resented.The scanning architecture was put forward based on the combination of the MTM bus communication agreement,and the state machines were desig ned in the master and slave module.Meanwhile,the communication protocol a nd program were realized between master and slave module.2)The hardware and software of test platform were designed.Through the development and experimental verification,a new solution was verified for the self-testing in digital-analog mixed-signal circuit.According to the test requirements,the design of the main structures of the test platform was realized,including the master LRM,AD conversion LRM,signal conditioning LRM,ARINC429 LRM and backplane.This thesis also designed the fault table and fault circuit nodes,and the corresponding scan chains to different scan standards.Finally,the software architecture of the test system was designed and programmed.3)Generation of test vectors.For the optimization of fault detection accuracy and the coverage metrics,the generation was researched about test vectors and responses.In details,the paper described the test vector generation process,thealgorithms of the net list parsing,BSDL parsing,link recognition,and vector generation,with their specific codes.