Research On Optimization Of Testing Cost Of 3D-SIC

With the intelligent development of the information age,the demand for high-performance integrated circuits is constantly increasing,and traditional two-dimensional chips are difficult to meet the development needs.The three-dimensional chip has the advantages of short global interconnect length,small area overhead,large bandwidth,low power consumption,and the like.It uses a large number of TSVs to vertically integrate multiple wafers of the same or different processes and can support heterogeneous integration.The vertical stacking method greatly improves the integration of transistors and the communication bandwidth between layers and is considered to be able to surpass Moore's Law.An important technology.However,large-scale use still needs to solve many problems.The three-dimensional chip test problem is one of the most important issues in these problems.Due to the complexity of the testing process and the high cost of testing,this dissertation establishes a test cost model for the three-dimensional chip test cost problem based on silicon through-hole bonding,and on this basis proposes a test cost optimization solution for binding neutralization and binding.The main work and innovations are as follows:From the perspective of optimizing the cost of the three-dimensional chip after binding,most of the existing solutions only take into account certain aspects and other shortcomings.In this dissertation,after the three-dimensional chip binding test cost problem,the test cost optimization algorithm is put forward under the combined constraints of test pin number,test TSV number and test power consumption on the binding test cost model including test TSV and test time.The problem of test scheduling is abstracted as the packing problem.When loading,the constraints are considered comprehensively,and as many chips as possible are tested in parallel to reduce the test time and optimize the test cost.Experimental results show that the proposed test cost optimization solution after binding can save a lot of test costs compared to similar solutions,and it has a lower test cost with few test resources.From the perspective of optimizing the cost of three-dimensional chip testing in the binding,only the testing time is optimized for the existing binding testing program,and the testing cost is rarely considered.This dissertation aims at this problem and establishes a binding in-test cost model including test TSV,test time,and failure increase cost.Based on the test cost optimization algorithm based on packing ideas,using greedy algorithm to optimize the stacking order can effectively reduce the test cost.The experiment found that the proposed test cost optimization program in the binding can effectively save a large amount of test costs compared to similar solutions,and that the test of a three-dimensional chip requires very little testing cost.