Research On The Test Generation Of Digital Integrated Circuits Based On PSO

With the development of the microelectronic technique, the scale of the integrated circuits becomes more and more large, and the structure becomes more and more complex, which leads to the test generation for digital integrated circuits becoming more and more difficult. Those traditional test generation algorithms are not applicable any more. Abroad and domestic scholars have come up with the GA's test generation algorithm. The algorithm is greatly efficient for some circuits because it decreases the test time and improves the test efficiency. But it is not universally efficient algorithm. The work proposes test generation method based on particle swarm optimization on the base of STPGThis dissertation selects the digital integrated circuits as research objects and uses the single stuck-at fault model. Regard increasing the fault coverage and decreasing the test time as goals. It proposes a new and structured simple algorithm—particle swarm optimization that is used to generate the test patterns of combinational circuits, initialize the sequential circuits, generate the test patterns of sequential circuits, optimize the test set of circuits. The main contents and contributions of this dissertation are as follows:1. Generates the test vectors for combinational circuits using PSO, which is compared to the ATPG based on GA. The experimental results demonstrate the efficiency —decreasing the test time and improving the fault coverage.2. Initializes the sequential circuits using PSO. PSO has inner parallelism and selection, so it can initialize much more flip-flops in much little time. The experimental results demonstrate the feasibility.3. Generates the test sequences for sequential circuits using PSO. The experimental results demonstrate the method can improve the fault coverage and decrease the test time efficiently.4. Compact the test set of the detected circuits using PSO. The number of...