A Low Power Power Management System For Passive RFID Tag Chip

The development of Internet of Things (IOT), biomedical engineering and logistics makes more and more higher requirements for the passive RFID tag. The low power and low cost design of passive RFID tag chip is the most effective approach to tackle this chal-lenge. The state-of-art are mainly focused on the low power design of the power dissipation building blocks of passive RFID tag. The power optimization of power management system of the chip is also needed to further develop. This thesis is aimed to design a low power power management system of passive RFID tag chip. Based on the careful analysis of the characteristics of the power consumption of passive RFID tag chip, a series of low power design techniques is proposed.Firstly, the block diagrams of passive RFID tag chip is introduced, mainly focused on showing the function and importance of power management system of the chip. Next, the system architectures of power management system is introduced. It is mainly consisted of three building blocks, i.e. rectifier, power supply generator and level shifter. The power and cost constrains of these blocks and their design guidelines are also analyzed.Secondly, a NMOS gate cross-connected HF rectifier compatible with standard CMOS process is introduced. The emphasis is focused on the design of a low power multi-voltage power supply generator. By effective control of various power supplies, the proposed power management system achieves 40% power reduction of EEPROM,59% power reduction of analog front end,27% area save of energy storage capacitor and 7μA current save. Next, a effective method is proposed to reduce the short time big current of the conventional level shifter.Finally, a multi-steps clock driving high-voltage generator is proposed, mainly focused on the choice of frequency, amplitude and steps of driving clock, and the design of core blocks, i.e. NCP-2 charge pump and amplitude controller. The design of NCP-2 charge pump is based on a power optimization method to determine the number of stages of charge pump. The number of stages of driving clock is 2, and the amplitude are 1.8V and 2.3V respectively. The proposed high-voltage generator can achieve 37.1μW average dynamic power consumption and 5.6nJ Power-Delay Product.