The Fpga Chip Esd Protection Design And Optimization

Electrostatic discharge is a common natural phenomenon, but in semiconductor industry it is one of the major incentives for IC failure, which brings about a great challenge to the reliability of the IC. As technology continues to scale, ESD issue becomes more and more severe, the ESD protection design has also become an essential element to the IC design.The content of this article is about the whole-chip ESD protection design for a FPGA chip, which is based on the0.25μm CMOS process and with multi-power mixed-voltage I/O. First, based on the ESD protection theory, the article introduces some basic concepts and principles of ESD protection design. After a thorough introduction to some experience and difficulties of the whole-chip ESD protection design, it raises the basic structure of the whole-chip ESD protection circuit. In the design of the Power Clamp, the author analyzes how the structural dimensions of the GGNMS affect the ESD performance, and describes the ESD-Implant and Silicide Blocking process. Based on a detailed analysis of various types of the I/O interface, subsequent content describes how an effective I/O interface ESD protection circuit is designed. Between the multi-powers the author designes an ESD discharge channel by the diode string. Here the author also describes how to depress the Darlington amplification effect of diode string, and ultimately improves the whole-chip ESD protection framework. At the end of the paper, the author pointes out the problems that should be noted in ESD layout and the details need to be optimized. Currently, the chip is not completed the tapeout. Since the effective ESD current discharge network between any pin of the chip, the ESD test results of HBM could pass2000V.The study successfully solved the problems of the ESD protection design for the FPGA chip, and posed the ESD structure with high capability. However, the simulation analysis and testing of the device and circuit are still inadequate, which will be continued to further intensify research in this area to improve the ESD protection.