1.8?3GHz SOI CMOS Power Amplifier Design

Power amplifier(PA)which is located at the end of the radio transmitter is one of the key components in the RF front end as the most power consuming unit,its efficiency has a significant impact on the overall power consumption.While application needs of global wireless communications are keeping raising new challenges,a more complex modulation scheme with high spectral efficiency is utilized in modern communication system(WCDMA/3G/4G/LTE)to reach high data rate and high transmission rate,Such as orthogonal frequency division multiplexing(OFDM)or quadrature phase shift keying(QPSK)and quadrature amplitude modulation(QAM)and phase shift/amplitude shift keying modulation combination,which put forward higher requirements to power amplifier which is one of the core components of the wireless communication system.Therefore,the design of high linearity,broadband RF power amplifier with high efficiency has been the focus of research.Based on 0.28?m SOI CMOS technology,this paper presents the design of 1.8-3GHz high linearity PA for mobile phone wireless communication system.Combined with the characteristics of SOI CMOS technology of high resistivity substrate,a stacked-FET structure is employed in the core circuit of power amplifier,where four transistors are connected in series to achieve high output voltage swing.In this study,a resistive voltage divider is used to provide proper gate biasing of stacked transistor in order to ensure that each transistor has the same gate-source and drain-source voltage.A relatively small external gate capacitance(C2,C3,C4)is introduced to allow an RF swing at the gate of each stacked transistor,this approach systematically reduces the drain-gate voltage swing of each transistor under large-signal operation in order to overcome the low breakdown voltage limit of MOSFETs.The input of the power amplifier using resistive lossy matching networks to achieve broadband characteristics,and a load pull method was adopted to figure out the optimized output load impedance.The whole design working includes circuit design,per-simulation,layout design and post-simulation.When the supply voltage is 6.5V and the operation frequency is 1.9GHz,the post-simulation results indicate that the PA achieves a linear power gain of 16.89dB with fluctuation is less than 1dB in the frequency range of 1.8?3GHz,the output power at ldB compression point is 26.63dBm,and a power-added efficiency(PAE)of 28.04%at OPidB.The power amplifier also achieves a saturated output power of 29.64dBm,and a maximum power-added efficiency(PAE)of 38.18%at 1.9 GHz.The power amplifier designed by this paper has excellent performance for each index,meet the mobile phone communication system requirements.Therefore,it can be applied to the transmitter front-end of the mobile phone wireless communication system.