Study And Design Of Highly Energy-efficient CMOS Power Amplifier For Mobile Terminal Applications

Power amplifier (PA) is the most power-hungry and nonlinear block in the whole wireless communication system, which determines the standby time and the communication data rate of the devices. So CMOS power amplifier with high energy-efficiency and high linearity has always been the research hotspot at home and abroad.It is a big challenge for linear PA design, especially for mobile terminal PA design, as the large loss of substrate, low breakdown voltage and various parasitic capacitance of CMOS process. Companies like Qualcomm have already launched products of CMOS PA which have a good performance in recent years. A CMOS linear power amplifier with high linearity and high efficiency is demonstrated in the first part of the thesis. It is designed for WLAN802.11g applications which is fabricated on TSMC0.18um process. The reliability and resources of the non-linearity of the PA are analyzed and the corresponding solutions are proposed. Then all of the bond-wires and lines on PCB are modeled by HFSS. The post-layout simulation results show that the PA can deliver output power of25.3dBm with33%efficiency at2.45GHz. In the test-bench of WLAN802.11g, the maximum linear output power which satisfies the requirement of EVM and spectral mask with a64-QAM stimulus is15dBm.As the current communication systems always adopt high-order modulation scheme, traditional PA always uses power back-off to meet the required linearity, thus decreasing the efficiency significantly. However, the digitally controlled PA(DPA) can make a better trade-off between linearity and efficiency. The research of DPA is shown in the second part of the thesis. The layout of the DPA is optimized for better performance. A new scheme for suppressing the second harmonic current and an improved LO driver are demonstrated. Two DPA are shown in the thesis:(1) a6-bit DPA for Bluetooth v4.0is designed on SMIC0.18um process. The post-layout simulation results show that the PA can deliver output power of4.3dBm with35%efficiency and the dynamic range of output power of the PA is26dB, which makes the PA support the EDR mode of Bluetooth v4.0.(2) An8-bit digitally controlled polar PA is designed on SMIC65nm process. The post-layout simulation results show that the PA can deliver output power of26.1dBm with42%efficiency at2.4GHz. The variation of the output power is less than1dB over a bandwidth of about900MHz.An active balun used in a power controller which is designed on TSMC0.18um process is presented in the third part of the thesis. Three stages of circuit for calibration and two circuits for bandwidth and temperature compensation are enrolled. The reliability and linearity of the MOS switch are analyzed. The post-layout simulation results show that, the amplitude error and phase error of the differential output signals of the balun are below0.2dB and1°respectively in1.9-2.6GHz. With the bandwidth compensation circuit, the gain variation of power controller is less than1dB over a bandwidth of about1GHz.