Research And Design Of High Voltage ESD Devices Based On SCR And LDMOS

With the close integration of system power application and IC industry,high voltage devices have been widely used in 4C products(computer,consumer,communications,and car electronics).In the high voltage integrated circuit,the lower limit of ESD(Electrostatic Discharge)design window is increased.The pursuit of the highest possible trigger voltage and holding voltage of ESD devices is an important goal of high voltage integrated circuit ESD protection research.Based on theoretical analysis and device simulation experiments,this paper studies SCR and LDMOS which is suitable for high-voltage integrated circuits ESD protection for the purpose of improving trigger voltage and holding voltage.Research includes basic ESD device theory analysis and TLP test,theoretical analysis and optimization design of SCR hoding state,theoretical analysis of LDMOS turn-on principle and holding state,and performance optimization design and analysis of NPN-LDMOS.The main innovations in this paper are as follows:1.Based on the high holding voltage characteristics of high-voltage ESD protection,two novel high-holding-voltage SCR structures(MHVSCR and SHVSCR)are proposed for the problem of low holding voltage of SCR.The high holding voltage paths of the MHVSCR and SHVSCR can cause serious loss of carrier in the SCR path,thereby suppressing the positive feedback of the two parasitic transistors and increasing the holding voltage.Based on the simulation results and theoretical analysis,it is concluded that when the high-holding voltage branches have more current or the branch holding voltage is higher,the device can obtain a higher holding voltage.The simulation results show that under the same size,the MHVSCR's holding voltage is 17 V,and the SHVSCR's hoding voltage with a higher branch holding voltage can reach to 20 V.2.A new improved scheme is proposed for the low-holding voltage problem of the strong robust NPN-LDMOS.The addition of an LVNW layer in the structure can result in a large number of recombination of holes injected into the base region of the device's parasitic path in the emitter region of the PNP transistor,resulting in an increase of holding voltage.Simulation results show that the device holding voltage can be increased by about 5V.3.A new improved scheme is proposed for the low trigger voltage problem of the strong robust NPN-LDMOS.In the improved structure,the reverse PN junction breakdown voltage increases as the doping concentration decreases.The voltage drop in the drift region is an important factor in the trigger voltage.The simulation results show that the improved structure increases the 30 V trigger voltage of NPN-LDMOS to 39 V.