Research And Design On All Digital Phase Locked Loop

Phase-locked loop is a kind of feedback control system,which is also called closed-loop tracking system.By using the phase difference between the output signal and the input signal,the output phase of the phase-locked loop can be adjusted automatically to make the frequency of the output signal track the frequency of the input signals.Both DLL(Delay-Locked Loop)and PLL are phase-locked loops,the main difference among them is that PLL has the voltage control oscillator but the DLL has the voltage control delay line.Depending on the composition,Phase-locked loops are mainly divided into two types:analog and digital.The digital phase-locked loop is more reliable,the chip area of it is small and it is easy to realize.Therefore,this thesis mainly studies the all-digital type phase-locked loops.In this thesis,a lot of work was done on the analyzing of the circuit integral function,such as the design of the logic circuit,the design and the simulation of the transistor level circuit and the optimization of circuit.Analysis and comparison of the structure and the working principle of DLL and PLL were completed in this thesis.According to the analysis of the DLL and PLL on the noise transmission performance which is one of the important performance indexes affecting the function of phase-locked loop,by analyzing the noise transfer function in each basic module's transmission,the noise power spectral density of the overall PLL and DLL is obtained and the characteristics of the DLL and PLL in the noise performance are compared.According to the analysis on the noise transfer function of the Components of the DLL and PLL,it is concluded that the noise transmission performance of the DLL is better than that of PLL.According to the advantages of digital circuit,the design of the all-digital DLL is employed.The design of the all-digital DLL which meets the design requirements was completed,and the frequency multiplying circuit and frequency dividing circuit for all digital DLL were realized.In this design the all-digital DLL adopts TSMC 55nm process,the design is carried out in three different operating environments:typical,best and worst.Finally,the area and resource consumption of the chip and the power consumption in that three conditions are obtained,the power consumption was 7.4649mW at lest.The working frequency range of the all-digital DLL in this thesis is from 100MHz to 500MHz,the shortest lock time is 2us and the area of the chip is 61456um2.