Study On Calibration Algorithm For Delay-line-based ADC

The traditional voltage domain-based ADC has a large area and power consumption.To reduce power consumption,it is an effective choice to switch from the voltage domain to the time domain.The quantization accuracy of the time domain improves with the progress of the process,and has now exceeded the quantization accuracy of the voltage domain.Delay-line-based ADC is a typical representative of time domain ADC,and in the occasion of ultra-high-speed sampling,Time-Interleaved technology can also be used to increase the sampling rate.However,the mismatch error of the delay-line-based ADC itself and the mismatch error between channels of the time-interleaved ADC greatly limit the dynamic range of the time-domain ADC,and a corresponding calibration algorithm needs to be introduced to improve its performance.This dissertation first systematically analyzes the error sources of the time-interleaved delay-line-based ADC and models it.The voltage-controlled delay unit of the delay-line-based ADC itself has a delay deviation,and there is also a problem of mismatch between the delay units;there is also a channel mismatch problem between the channels of the time-interleaved ADC.Besides,this dissertation expands the harmonic correction algorithm(Harmonic Distortion Cancellation,HDC)in the pipeline ADC,and applies it to the delay-line-based ADC to achieve the calibration of delay mismatch.The algorithm structure is improved in this dissertation.By adding an additional delay chain ADC as a reference channel,a pseudo-random sequence used for calibration is injected to help quickly extract errors and reduce calibration time.Finally,a method based on chopping modulation is used to simultaneously calibrate the bandwidth mismatch and the timing mismatch between channels.Aiming at the problem that the calibration direction of this algorithm sometimes changes with the input signal frequency band,which leads to the failure of calibration.A calibration direction correction algorithm is designed to expand the range of application of calibration.Based on MATLAB/simulink,a 4-bit,200MS/S,two-channel time-interleaved delay-line-based ADC model was built to verify the structure and function of the time-interleaved delay-line-based ADC.Besides,an 8-bit,100MS/s delay-line-based ADC was built to verify the single-channel internal error calibration algorithm.For the single-channel harmonic distortion calibration algorithm,when the third-order error coefficient of harmonic distortion is 0.05,it is calibrated by the calibration algorithm After that,ENOB rose from 5.5 to 7.64.In addition,a four-channel,12-bit,1GS/s TIADC was built to verify the time mismatch error calibration algorithm between the channels.When the second,third,and four channel timing mismatch errors were 3%,1.5%,-0.4%,after being calibrated by the improved chopping modulation calibration algorithm,ENOB is increased from 6.61 to 11.89 bits.In addition,in the first to eighth sub-Nyquist bands,the correctness of the calibration direction correction algorithm is verified.The RTL design of the calibration algorithm is also carried out in this dissertation.Verilog HDL is used to describe the calibration algorithm.Modelsim is used to complete the function verification of the calibration algorithm,and the performance verification of some critical algorithms is further completed on the FPGA.