Research Of Low Noise Readout Circuit For Infrared Focal Plane Arrays

Since the invention of infrared imaging detection technology,it has been applied to all aspects of the military,and has also attracted much attention in the fields of health care and equipment testing.With the continuous development of infrared imaging technology,Infrared Focal Plane Array(IRFPA)has gradually been paid attention by researchers at home and abroad.The IRFPA imaging system mainly includes two parts: a detector cell array and a readout integrated circuit(ROIC).With the continuous advancement of integrated circuit industry technology,the scale of pixel arrays has continuously expanded,and the pixel size has been continuously reduced.The performance of ROIC has become a key factor that restricts the development of IRFPA imaging systems.Therefore,research on high-performance ROIC is of great significance.Firstly,This thesis makes a brief analysis of the research progress of IRFPA technology.According to the circuit type and working principle of ROIC,comparing different circuit types,Capacitance Transimpedance Amplifier(CTIA)is selected as the pixel circuit type designed in this paper.Secondly,the theoretical analysis and design simulation of the CTIA-type pixel circuit are performed,and the various performance parameters of the pixel circuit are considered,especially the processing of the noise is introduced and analyzed in detail.In order to reduce the input reference noise,the relevant double-sampling CDS circuit is added to the interior of the pixel during the design process.Although the power and area of a single pixel are increased,the processing of the column-level signal is simplified,and two signals are eliminated.The problem of interference in the column bus transmission process is conducive to the layout of the overall chip.Again,the other modules of the readout circuit of the IRFPA have been theoretically analyzed and designed and emulated,and the design of the digital control module has been highlighted.The function of the digital control module is to implement 32 × 32 pixel array row and column selection and various output modes and integral mode control,including full array readout,windowing readout and subsampling readout.This paper adopts row-by-row scanning method of preselected and then selected,and proposes a pre-established mechanism,which not only improves the readout rate of the circuit,but also reduces the overall power consumption of the system.Finally,this paper uses the 0.18?m CMOS process.The ROIC pixel array has a 32×32 frame rate and a frame frequency of 100 Hz.It supports one,two,and four output modes.The read rate is 20 Mbps.The overall area is 2.2mm x 1.6mm.This article uses a full-custom method in the design process.The layout and layout of the overall chip are optimized,and the DRC and LVS are verified.