Design And Implementation Of High-Speed Video Signal Bridging System Based On CPLD

With the development of semiconductor technology and manufacturing technology and people in the pursuit of high-definition video,the traditional image sensor interface is gradually converted from parallel interface to high-speed differential serial interface such as CSI,LVDS.As a result,the problem of mismatched video interface types between sensors and processors has become increasingly prominent.On the other hand,the original video data and processor ISP processing capacity does not match and this problem also needs to be solved urgently.In response to the above problems,this thesis proposes a video bridging scheme based on programmable logic device.The conversion from serial interface to parallel interface is one of the research topics of this thesis,in addition,this thesis focuses more on achieving the following two aspects:on the one hand,this scheme realizes that a single ISP supports two image sensors and maximizes the processing capacity of the processor ISP.On the other hand,the scheme realizes the conversion of single ultra high resolution video to multiple lower resolution video,and the problem that single ISP cannot deal with ultra high resolution video is solved.The bridge system is designed to provide more solutions for processors with low bandwidth parallel video interfaces.In summary,the main work and achievements of this thesis are as follows:(1)The development status of CMOS image sensor interface is investigated and the current research status of video interface bridging scheme is analyzed.Besides,the feasibility analysis and logical resource evaluation of the bridge chip are also given in this thesis.(2)Based on the binocular depth camera for specific application case,the correctness of the dual-sensor video bridge module design is verified,including CSI-2 serial-to-parallel conversion,binocular synchronization and merging module.The frequency reduction module is designed to solve the sensor and processor transfer rate mismatch problem.The experimental results show that this scheme achieves the simultaneous transmission of dual video,so that the processor with a single ISP and parallel interface simultaneously supports two serial video signals and gives full play to the ability of the processor ISP to process two channels of video.(3)Python 1300 image sensor is used as a specific application case,a dual-channel high-speed serial LVDS signal deserializer is designed to restore the parallel transmission of the original video data This thesis uses the method of image cropping,which extracts pixels by block and achieves single-channel high-resolution video to dual-channel low frame rate video transmission.The problem that the processing capability of processor ISP and the amount of video data is not matched in the process of high-speed video acquisition is solved.Simulation results show that the scheme can be extended to ultra-high resolution video capture.(4)The Lattice's MachX02 platform is selected to realize the overall hardware design of the video bridge system.According to analysis,this thesis completed the system power,image acquisition,image output and design of other hardware module,correspondingly,draw the high-speed digital circuit board and complete the circuit board debugging.The test of each hardware module shows that the system can be stable and reliable operation.