Gigabit Ethernet Network Interface Adapter IP Design Based On AXI 4.0

With the coming of the smart generation,the Gigabit Ethernet will become the main requirement of electric devices such as high-definition digital TV instead of 10 M Ethernet and 100 M Ethernet.This design aims to provide a complete and referable design procedures which is about the Gigabit Ethernet based on AXI4.0 bus protocol.At the beginning of this article,the history of the Ethernet and the development of AMBA bus protocol is introduced.The function of GMAC module,package producer module,DMA engine and the AXI controller are put forward in this article.At first,the design of sendSTM and receiveSTM of GMAC is given,the FIFO module is added after the analysis of application;after that,the design of package producer module which contains TCP segment offload,checksum,IP check which can reduce the load of CPU is given in this article,in addition,4 channels which is used to differ priority;furthermore,the design of the DMA engine and its interface signal is fully described and the design of 4 DMA channels is provided in this thesis;finally,the design of verification platform which is based on UVM is given,this verification platform is built for the Ethernet,also,some verification model of some modules such as GMAC,DMA,package producer and AXI controller are provided in detail,and the simulation waveform is shown in this thesis.The design of the IP in this thesis is proved to be reliable and feasible after several tests and experiments.Also,theis IP is applied in some SoC.So,the design flow and the design method can be a reliable reference to the SoC engineer and be further expanded.