Research And Implementation Of Adaboost Face Detection Algorithm Based On FPGA

Face detection comes from the combination of biometric technology,computer image processing and pattern recognition.Since put forward,it has been a popular research topic in machine vision.There is a wide range of demand for it in public security,defense,customs,transportation,finance,social security,medical,and other civilian security control.Adaboost face detection algorithm studied by this paper,has the best overall performance in single face detection algorithm.Adaboost algorithm is widely used in PC and many other devices.Because of its relatively complex calculation process and high time and space computational complexity,there has been only a little study done on hardware design for Adaboost algorithm.This design uses FPGA to implement Adaboost face detection algorithm and introduces the SOPC method to design the entire system architecture.All the computing and control tasks are integrated into a single FPGA chip.With just a few more chips,we can build a complete face detection system,which greatly reduces the cost and improves the practicality in the embedded field.For the part of Adaboost face detection algorithm which requires a lot of computing,we can use pipelined architecture and parallelism of hardware to speed up the processing algorithms.For the control part,we can take advantage of the flexibility and scalability of software and arrange the work process reasonably so that each module can work methodically.In this paper,the main work includes the following content:1.First of all,the advantages of domestic and international human face detection algorithm is described.After analyzing the principle and implementation of the algorithm and writing program to train the parameter of the algorithm with the matlab software,the needed weak classifier,strong classifier and other parameters is found out.By discussing,a scanning method is adopted to implement face detection on FPGA.2.The Altera DE2-70 board is used to study the algorithm.Then the driver program is written or parameters is set for the SSRAM,SDRAM,SD card,VGA interface and other chips.3.On the development board,the data of the bmp pictures to be detected are read,decoded,grayed,used to compute integrals and stored in hardware,preparing for the executing of detection and calculation module.Then the modules are designed to have the detected results stored,merged,calculated and finally displayed on the monitor.4.Combining algorithm principle,the detection window data update module is designed.The pipelined architecture and the parallelism of FPGA are used to accelerate the detection window calculation.The finalized human face detection system,for an image whose size is 320*240,with system clock of 100 MHz,takes 86.1ms on average to complete the detection process,11.6 frames per second in speed.