Design Of Data Synthesis Timing Module With 3.35Gbps

As an important test instrument in the test field,the timing data generator can output pulse signals with variable data rates,pulse widths,amplitudes,work modes,and trigger modes for the device under test,and output pulse sequences that can be edited arbitrarily by the user.This paper conducted relevant research with the goal of the high-speed data synthesis and pulse synthesis technology,and achieved the data rate range of serial data synthesis of 50 kbps ~ 3.35 Gbps.The storage depth of main sequence which length is 8000 rows reaches up to 512 Mbits.The main sequence contains up to 50 subsequences and each subsequence contains at most 256 rows of data blocks.In the data block unconditional jump,event jump and trigger wait function mode,data synthesis module can achieve data block repeat output,single output and other functions.The main function of the digital synthesis module is to design and complete the entire timing system under the premise of guaranteeing the function of the timing data generator,to realize the indexes and performance of the data synthesis part,and to improve the module design.The specific work includes:1)Analyze the analysis of system design requirements,determine the overall design plan for 3.35 Gbps data synthesis,and analyze the design difficulties.2)Digital synthesis module sequential circuit design and hardware circuit design: high-speed pulse data communication circuit design;independently storage and reading different types of data with a combination of SRAM and DDR3 SDRAM;generation of the high-speed data with a combination of FPGA internal high-speed serial transceiver and the parallel-to-serial conversion circuit;the pulse synthesis with a combination of a high-speed counter wide-range delay and a delay line fine delay,and a picosecond delay stepping technique.3)Analysis of the key issues of the digital synthesis module: the graphics data is converted from the PCIe local bus 32 bits width to the DDR3 data bus 512 bits and the write address is assigned to it;the asynchronous FIFO is used to convert the DDR3 burst output uneven data into even data;the use of FIFO and OSERDES and transceivers to convert parallel data to serial data stream with a frequency-varied design;graphics data address generators implement unconditional jumps and event jumps of data block rows in the main sequence containing subsequences;the dynamic switching control timing of GTX high-speed serial transceiver serial data rate.4)Digital synthesis module testing and result analysis: Joint debugging and improvement of timing logic and hardware circuit design,testing of digital synthesis module,and implementation of project functional index requirements.This article successfully completed the above work.After the design and debugging,the digital synthesis module achieved a variety of functional modes with the 3.35 Gbps sequence pulse signal generation,completed the related functional specifications requirements of the digital synthesis module of the timing data generator.