Synthesis Of The High-speed Pulse And Pattern Design

Timing data code generator is an electronic test device or software used to generate digital level excitation.It can be a source of synchronous digital excitation.The signals generated are of great help to digital electronic devices tested at the logical level.Based on the project of "3.35 Gbps timing data generator",this paper realizes the module of deep storage seamless data signal generation.The main indicators include: the output data rate of the signal is 50k~3.35 Gbps,and the storage depth is 512 Mbits.This paper mainly realizes the following functions:1)Deep memory circuitThis design based on DDR3 SDRAM deep storage circuit,including the needs of design method of obtaining data block storage method based on FPGA internal SRAM,and the interface design of DDR3 SDRAM deep storage circuit,interface includes MIG nuclear interface design and the clock interface design,finally designs the DDR3 SDRAM deep memory read/write timing,including the control of state machine design,and write and read sequence state machine design.2)Pulse data synthesis circuit based on synthesis and decompositionThe circuit structure of data synthesis output is designed,pulse synthesis circuit and data synthesis circuit are designed,controllable pulse width synthesis is realized by using delay circuit,digital pulse width synthesis,NRZ and RZ code signals are realized by means of synthesis and decomposition,and the output of R1 signal is realized by means of reverse output method.3)Communication circuit based on PCI-eThis design proposes a communication circuit based on PCI-e,including PCI-e's hardware interface circuit,PCI-e's DMA data transmission mode,and local FPGA's local bus interface method.4)Rate synthesis method of deep storage dataThe low frequency data stream synthesis method and the high frequency data stream synthesis method are designed.The low frequency data stream synthesis method is realized by using the logic resources inside FPGA,and the low frequency data stream is generated by counting synthesis method.The synthesis of high frequency data flow through the FPGA internal high-speed serial transceiver GTX,GTX with the highest output is 12.5 Gbps,required in the design of the highest data rate is 3.35 Gbps,thus can satisfy the requirements of the need,in this section of the structure of the GTX and reset sequence are introduced,and based on the structure needed to set up the power supply module,also according to the reset sequence,designs the GTX state machine,guarantee the restoration of normal,provide guarantee for changing the data flow,ensure the normal order of the data to be able to send and receive,as far as possible don't appear error and data loss.In this paper,the circuit and method described above were debugged and verified,and the timing function of the project was completed.