Design Of Signal Processing System For One Soldier Radar Based On FPGA

With the development of radar systems,system integration has become more and more higher,and signal processing design based on FPGA has become a trend.At the same time,the huge amount of radar data needs to meet real-time processing and transmission requirements FPGA has parallel performance and high-speed clock performance characteristics,can meet the radar signal processing real-time and large bandwidth requirements,and achieve radar processing functions and hardware acceleration.Based on the specific background and requirements of a single soldier radar project,combined with the features of FPGA parallel processing architecture,this thesis analyzes and studies the architecture,concrete implementation method and performance analysis of the radar signal processing system.The system includes 8 IPs including GTH,ROCKETIO,RAPIDIO high-speed serial interface,DDR read/write interface,digital beam forming(DBF),pulse compression,MTD,CFAR operation module,etc.All computing modules comply with the AXI bus protocol and will each The modules are combined into an algorithm chain,and the system supports dynamic switching of multiple working modes.The system architecture adopts a modular design concept and parallel data flow processing methods to construct three data flow channels.Each channel has its own independent control flow,data flow,and status monitoring flow.Channels are independent of each other,and their architectures have easy algorithms.Chain expansion,debugging and versatility features.The radar signal processing system eliminates unwanted clutter by the desired target signal and extracts target information.The echo data is first subjected to strong and narrow pulse rejection processing,rejecting strong and narrow pulse interferences with large SNR,and then performing pulse compression processing(PC).The pulse pressure data is processed in anti-asynchronism and then the anti-asynchronous data is subjected to moving target detection(MTD)processing to eliminate clutter interference such as fixed clutter and weak weather,and the processed data is subjected to constant false alarm(CFAR)and residuals.Clutter map,target detection and other processing,further suppress residual clutter and control false alarm rate.The zero filter data output by the MTD process is used for tangential detection,and the result of the tangential detection is ORed with the conventional detection result to obtain the detection result of a single channel.Finally,the data information of the over-detection thresholds of each channel is extracted,and information tables are formed according to the agreed format to send to other subsystems.The radar FPGA design is based on the high-performance Virtex7 series XC7VX690 T chip.According to the "top-down" idea,the main technical indicators related to DBF and signal processing are modularly designed,and the logic synthesis,simulation,timing analysis and implementation of each module after the design is completed.Then,the functions of each module are optimized,verified by simulation,and downloaded.This ultimately results in a streamlined radar signal within a single FPGA chip.The total hardware resources accounted for more than 60% on the FPGA V-7 690 T with a clock frequency of 200 MHz.This design has achieved the expected performance index and can be widely used in radar integrated processing subsystems.