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The Design And Implementation Of CFAR Development System Based On FPGA

Posted on:2017-05-25Degree:MasterType:Thesis
Country:ChinaCandidate:J N WangFull Text:PDF
GTID:2348330512969652Subject:Engineering
Abstract/Summary:PDF Full Text Request
At present,the implementation of CFAR(Constant False Alarm Rate)algorithms based on FPGA development platform is inefficient and less engineering-realizable due to the lack of a common CFAR resource base.In order to improve the development efficiency of CFAR,and meet the basic requirements of radar signal processing,this paper proposed to design an FPGA-based CFAR development system.This paper first established an overall design scheme for system development in accordance with the basic requirements and functionalities of the development system.It mainly includes two parts:FPGA hardware development platform and software development platform.FPGA hardware development platform provides verification for the chip dedicated to algorithm processing by CFAR and a communication interface for radar acquisition.The software development platform is used to develop various modules needed in design and realize the calls of the modules,for finally implementing the CFAR algorithm in demand.Specifically,the design of CFAR resource base is the focus of this design.The goal of system development is to realize the modular design of CFAR algorithms,and select different algorithm modules according to different types of CFAR algorithms for lap-jointing to generate different CFAR algorithms.This paper primarily researched the basic structure of ML-CFAR and OS-CFAR,summarizing mathematical models for these two CFARs.ML-CFAR algorithm includes N-tap buffer unit,protection unit,summation unit,maximum unit,and minimum unit.OS-CFAR includes sorting machine model and statistical counting model.To ensure that CFAR processor could adapt to different radar data formats,this paper designed data matching aided modules consisting of bit width extracting module,frequency division model and bit width conversion module.A communication interface was set up between FPGA development platform and computer in the design,completing the logical design of UART,and realizing the storage of processed data in computer.The test showed that every functional unit met the design requirements.Finally,tested signals were used to verify the rationality and correctness of system design,and meanwhile hardware and software interfaces were set apart for the follow-up development.
Keywords/Search Tags:FPGA, Building Block Design, CFAR Algorithm System
PDF Full Text Request
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