Design Of Radar Moving Target Detection Based On FPGA

Working in a complex electromagnetic environment,, radar is always influenced by kinds of clutter. In order to pick out the desired targets, it is neceesary to restain the clutter., such as Moving Target Indication, Moving Target Detection, clutter mapping technique and constant false alarm rate. Since the high speed processing and big band width of FPGA, FPGA can process the radar data in high speed coordinating with DDR3.This paper emulates theory about moving targets, and gives methods in engineering realization. this thesis mainly concentrates on the following points.1. Beginning with the theory of line frequency modulation continuous wave radar, Moving Target Indication(MTI) technology is emulated, which eliminates the fixed ground clutter and gives the realization and relative merits. The paper also introduces the Moving Target Detection(MTD) technology which eliminates the moving clutter, and two kinds of Doppler filter bank are compared. four kinds constant false alarm reciver methods is given. By using the information of zero speed channel, the clutter is designed, and the super clutter detection is created. The doppler clotting technique and the realization in engineering is introduced.2. The paper introduces the hardware processing platform and gives a structure chart. The bandwidth of this platform is big enough, to satisfy the need of data transform. Then FPGA resource is introduced, which is high logic density, low power requirements and programed repeatedly. FPGA uses the technology of streamed processing, which can reduce the delay and promote the speed of signal processing. FPGA has more logic cellsand more Embedded Multipliers, which can evolve signal processing with high efficient. The history, the development and the use of DDR3 are detailed presented in the paper. The memorizer of FPGA is limited, during the signal processing the system needs store much data. DDR3 is the best choice for its high speed and big volume, which can cooperate with the FPGA to reach the goal of data store.3. The radar target detection scheme is introduced. And the structure charts of MTI,MTD, CFAR, super clutter detection and doppler clotting are aslo designed in the paper. While controling the DDR3, the function of data reorder is added. By controlling the address of DDR3 and the ram, data reorder is realized, which reduces the time of signal processing.4. The reuslts of detection and reliability of implementation are analyzed with real radar data, which means that the funcion of FPGA is verified to be true. This paper is concluded in the end, and the advices are given to improve the capability.