Research And Implementation Of Fast Convergent And Full Band Sampling Time Mismatch Correction Algorithm

The analog to digital converter(ADC),which serves as a bridge to simulate the world of the world and the digital world,play an important role in modern electronic systems.However,with the development of technology,the digital system is becoming more and more demanding for the analog to digital converter.The traditional ADC architecture is difficult to meet the requirements of high speed and high precision,and the appearance of time interleaved ADC makes the design difficulty of high speed and high precision ADC greatly reduced.Through multi channels parallel operation,the sampling rate is doubled,and the theoretical accuracy is the same as the single channel.However,the mismatch between channels makes the precision greatly reduced,especially the mismatch of sampling time,which is not only complex,but also difficult to correct,so it become a hot topic in the study.But most of the research is focused on the first Nyquist region,and there is less research on the algorithm that can be applied in full band and fast convergence.Based on the above shortcomings,this paper presents a sampling time mismatch correction algorithm which can be applied to the whole band and converges fast.The algorithm is based on direction determination and bisection method,and is implemented in a combination of digital domain and analog domain.The algorithm flow is mainly divided into error detection and error correction stage.In the error detection stage,based on the direction decision algorithm,the algorithm uses digital circuits completely,it can accurately determine the direction of sampling time mismatch in the full band range,and provide direction information for error correction.In the error correction stage,based on the bisection method,the algorithm uses digital circuits to gradually iterate out the delay value of the feedback delay chain,and provided to the analog circuit to adjust the delay of the sampling clock in each channel through a capacitor array.It takes only ten correction cycles to converge.Finally the algorithm achieves the purpose of the time mismatch of the full band fast correction sampling time.Because the wide use of digital circuit implementation,and the algorithm contains only addition operations,without complex multiplication,and the feedback delay chain that regulates the phase of the sampling clock consists of only a number of capacitors and MOSFET switches.So the algorithm can be easily implemented,and the hardware complexity is low.It is convenient to design the digital circuit for the algorithm through the Verilog language.The algorithm is simulated later.Through the model simulation of a 12 bit two channel time interleaved ADC we can know that when the timing mismatch is 13.35 ps and the input signal frequency is 133.79 MHz,the SFDR increased from 45.03 dB to 87.8dB,and the ENOB increased from 7.19 bits to 11.81 bits after calibration.In the same situation,when the input signal frequency is 1276.4MHz,the SFDR and the ENOB are 74.08 dB and 11.45 bits,increased by 48.66 d B and 7.52 bits,respectively after calibration.