Design And Implementation Of FPGA Configuration Interface For A Digital Processing Platform

With the popularity of the Internet,the development and innovation of wireless communication technology.Nowadays,the field of wireless communication is the coexistence of a variety of communication systems and communication systems.The requirement for digital processing is getting higher and higher.More and more complex algorithms achieve at higher speeds and lower costs,including FFT,wavelet transform,digintal filter and so on.Everyone has some structural elements that can be implemented in parallel methods.The architecture of FPGA can effectively implement parallel operation and improve the efficiency and speed of the algorithm.Based on a digital processing platform,this paper designs and implements the data transmission and control of the FPGA related hardware devices on the platform.And an effective scheme is proposed to enable FPGA to efficiently manage the resources on the digital processing platform.When the user is using the digital processing platform,the hardware resources of the platform can be adjusted according to the corresponding command.This function makes users more focused on the implementation of digital processing algorithms,and does not have to spend a lot of time on the hardware transmission interface of the digital processing platform.Based on this,the thesis has completed the following aspects:First,a simple Ethernet transmission protocol is implemented.The implementation of a simple UDP protocol on FPGA is given.The function of data transmission through the network port is realized by the PC and the digital processing platform.The function of Ethernet interface is refined,which is divided into data transmission and configuration data transmission,and paving for the follow-up work.Second,the Ethernet J-TAG function is realized.The FPGA code is loaded by the J-TAG protocol through the network port.Third,according to the hardware condition of the digital processing platform,a set of effective clock network management scheme is designed and implemented.The user can control all the clock resources on the platform efficiently by configuring the command.The work of this paper is designed and implemented for the FPGA configuration interface on a digital processing platform.The research results have been verified by engineering,which has practical project value and engineering reference significance.