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Research And Development Of EPA Protocol Stack Based On FPGA

Posted on:2009-12-30Degree:MasterType:Thesis
Country:ChinaCandidate:X F ZhangFull Text:PDF
GTID:2178360242492148Subject:Detection Technology and Automation
Abstract/Summary:PDF Full Text Request
At present,the realization of EPA stack is based on ARM embedded processors and embedded operating system such asμC/OS-Ⅱ.There are many problems existing in the software implementation,such as the precision of clock synchronization is not high enough,the communication schedule performance is not fully exerted,still the stability of the protocol stack needs to be strengthened,etc.EPA communication chip is a good way to solve these problems.Currently,chip-designing often implements the function of chip,completes the development and validation of prototype chip on FPGA first.Based on an in-depth study of the principle of EPA standard and its hardware realization method,this paper proposes a FPGA-based realization method for EPA protocol stack.The main achievements and innovations are listed as follows:1.A development board for the EPA protocol stack is developed.It uses the ATMEL AT91R40008 microcontroller and ALTERA CycloneⅡFPGA as main controllers.Driver for the Ethernet card AX88796L based on this platform is developed.2.The PTP synchronization algorithm is designed.A frequency compensation algorithm based on the weighted least-squares algorithm is proposed.This algorithm adopts the frequency compensation algorithm to adjust the time drift between PTP synchronizations,and the weighted least-squares algorithm is introduced to calculate the dynamic compensate value.Test results show that the algorithm has greatly improved the synchronization accuracy of PTP,and the accuracy reaches lus.3.The EPA communication schedule algorithm is devised.To solve the problems of large memory footprint and low lookup efficiency existing in the software implementation method for EPA communication schedule algorithm,a hardware implementation method based on FPGA is proposed.This method adopts a strategy,in which messages are stored intensively and communication schedule lists are constructed separately.A lookup scheme of the communication schedule lists based on parallel processing is devised.Test results show that this implementation method decreases the consumption of memory resource,enhances the message lookup efficiency by 9 times,and doubles the performance of communication.
Keywords/Search Tags:Industrial Ethernet, Ethernet card driver, clock synchronization, communication schedule, FPGA, EPA
PDF Full Text Request
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