Research And Implementation Of Design Compiler Topographical Technology In The Quad-core LEON3 Processor Chip

With the development of integrated circuit technology,the geometric size of the circuit is getting smaller while the scale of the design is getting bigger,and the interconnect delay gradually occupies the important position in the critical path,dominating the path delay.Wire load models,which were used to compute the interconnect delay in the traditional synthesis process,are inaccurate in modern process and make great differences between the results of synthesis and post-layout.Design Compiler topographical technology,provides a good solution to improve the consistency of results before and after automatic placement and routing.At the same time,the routing congestion problems are more and more prominent in physical design,and it is necessary to make further optimization to solve the routing congestion problems.To solve the problems above,in this paper,Design Compiler topographical technology is used to generate an optimized gate-level netlist,and an algorithm is proposed to optimize the routing congestion problems in physical design.On the basis of above,the design optimization of quad-core LEON3 processor chip(L4P chip)is achieved.Firstly,L4 P chip is synthesized using Design Compiler topographical technology(DCT).Design Compiler topographical technology computes the interconnect delay accurately by adding physical constraints in synthesis process.Based on the data preparation,the hierarchical synthesis flow is used to synthesize the L4 P chip,and the results are compared with the results of the traditional synthesis method.Secondly,an algorithm(RCO)is proposed to optimize the routing congestion problems.Considering the routing congestion problems in physical design of single-core LEON3 processor chip(LSP chip),the traditional solutions are improved and optimized.By comparing the effect of the traditional solutions and the RCO algorithm,it is shown that for the same congestion region,the standard cells are distributed more evenly by the RCO algorithm,and there is no congestion at the boundary of the region.Finally,the physical design of L4 P chip is achieved.Based on SMIC90 nm 1P9M technology,using automatic placement and routing tool named IC Compiler,following the hierarchical physical design flow,L4 P chip is designed.Compared to the results of the traditional synthesis method,the results of this paper show great optimization in timing,area and power consumption,which indicates DCT and RCO are effective in improving the correlation between synthesis and post-layout.This paper applies DCT technology and innovative RCO algorithm in the actual L4 P project to optimize the results of chip design.The research of this paper has great reference significance in the research and application of multi-core chip physical design.