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Design And Implementation Of The High-speed Data Acquisition System

Posted on:2019-03-13Degree:MasterType:Thesis
Country:ChinaCandidate:Q Y GuoFull Text:PDF
GTID:2348330545962545Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
High-speed data acquisition is a very important prerequisite for maintenance of communications equipment and failure analysis,because having data means that you will have the power to speak.In this paper,high-speed data acquisition system is mainly based on the scientific research projects in my laboratory,and take the mature technology as the support.Its main task is to complete the automatic monitoring of train communications equipment,because of uninterrupted manual records and data analysis will inevitably lead to unnecessary costs in terms of labor costs and time costs.And where the greater the data needs,there should be fewer human factors involved.The most important part of this paper is the hardware and software design.During the design process,we first conducted a survey on the status of data acquisition system from the domestic and foreign development,and then we complete the architecture design of the data acquisition system according to the maturity of the corresponding technology and the comparison of the similar technologies.Acquisition system architecture is mainly based on FPGA,and automatic gain control,analog-digital conversion,DDR2 SDRAM and Gigabit Ethernet are used as the external circuit.When the requirements of the overall design on acquisition system and the options of corresponding technical become clear,we completed the chip selection,hardware schematic design and high-speed PCB design.In the design process,we also simulated and verified the filter,AGC and other circuits.As for FPGA software design,Cyclone V E provides the user with the soft core of Gigabit Ethernet MAC and hard core of DDR2,so it can reduce the time of developing low-level driver code in the software design.According to the requirements of the acquisition system and the data sheets of the above two IP cores,this paper finally completed the overall architecture of the software and completed Verilog code design for different functional modules.The verification of function and system test of the acquisition system are the key to ensure the normal working of the system,and we completed the closed-loop test of the acquisition system from the signal sampling to the data monitoring on PC through the rigorous verification means.In summary,the high speed data acquisition system is finally realized,and the system can work steadily in the actual working environment...
Keywords/Search Tags:high-speed acquisition, fpga, agc, ddr2, gigabit ethernet
PDF Full Text Request
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