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Design And Implementation Of The High Frame Rate Image Compression Device Loaded On Rockets

Posted on:2019-03-25Degree:MasterType:Thesis
Country:ChinaCandidate:M H LiuFull Text:PDF
GTID:2348330545491838Subject:Engineering
Abstract/Summary:PDF Full Text Request
The rapid development of remote sensing technology has made it possible to obtain the effective data through remote sensing satellites,and also greatly promotes the development of military and national defense.Because the data obtained by the remote sensor needs to be transmitted to the ground in real time,and with the continuous improvement of remote sensing image resolution,the amount of data that needs to be acquired and transmitted increases dramatically,and the difficulty of space-to-earth data transmission also increases.The demand for remote sensing image data transmission can not be satisfied only by improving the transmission bandwidth,and it must be processed by data compression technology.Therefore,the research of high frame rate image compression device based on arrow has important practical significance.This paper firstly introduce the principles of image compression and image compression standards,and provides theoretical support for the design of the system.Through the investigation of the domestic and foreign existing arrow-based image compression technology and the comprehensive consideration based on the system function requirements,identified the architecture of FPGA and the special JPEG2000 codec chip ADV212 which are the main control chip and core structure,and designed and implemented the high frame rate image compression device.The overall scheme of the image compression device is designed,and the hardware and logic design of the image compression device are mainly completed.Taking the system solution as the core,according to the selected chip and working mode of the hardware circuit design part,the circuit schematic including the image acquisition,storage and compression modules and the PCB design are completed.The functions of the modules such as image acquisition,storage,compression and transmission are designed and implemented through VHDL hardware description language.Based on this,the system test platform is builtFinally,the system is tested by the system test platform,and the test results are analyzed.It is verified that the image compression device can achieve image compression up to 100 frame /s.The reliability analysis of the device was performed to ensure that the device can work normally in the context of an on-board application.The results show that the image compression device designed in this paper can process image data in real time and meet the system requirements.
Keywords/Search Tags:Image Compression, ADV212, FPGA, JPEG2000
PDF Full Text Request
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