| Small size effects have become limiting factors for the development of MOS device,so the FDSOI(Fully Depleted Silicon-on-Insulator)MOSFET that gives predominant electrical characteristics and smothers short channel effect(SCE)is regarded as the best among candidates of MOS devices.With the characteristic size of the MOS device develops into nanometer scale,it prompts an exponential ascent in the direct tunneling current and damages the conduction characteristics of the device.Along these lines,it is one of the principal undertakings to choose the suitable high k material instead of SiO2 as the gate dielectric layer.Nonetheless,high k gate dielectric additionally has its problems.There are considerable measures of interface fixed charges and interface traps between the high k dielectric and the silicon film,these problems reduce carrier mobility and make the curve of C-V characteristics distortion.And after that,the FIBL(fringing induced barrier lowing)effect is caused by the electric flux lines moving through the boundary because the physical layer of the high k gate is too thick,and the device characteristics is reduced.Therefore,the immediate presentation of the high k gate causes the drift of threshold voltage and the decrease of current drive capacity while the SCE is suppressed.Researchers suggested a bulk silicon MOSFET with a low k buffer and utilized a thermal dynamic model to calculate its threshold voltage.In this thesis a stack gate of high k and SiO2 was applied in the FDSOI MOSFET with SiO2 as the low k buffer(named high k+ SiO2 gate in the following description),the characteristics of the threshold voltage and DIBL(drain induced barrier lowing)were subsequently discussed.Because of the complex structure of SOI MOSFET,its drain electric field,source electric field,front gate electric field and back gate electric field are coupled with each other,which directly affects the gate surface potential.The accuracy of traditional one-dimensional model is low,but the process of numerical solution is complicated,and the cost of computation is too large.Therefore,the threshold voltage model is established by solving the two-dimensional Poisson equation and Laplace equation.In this thesis,we consider the stacked gate and the physical materials of different properties,and introduce the equivalent rectangular source.The SOI MOSFET is equivalent to four rectangular sources,and the boundary conditions of the four regions and the connection conditions are established.The Separation of Variables Method obtained the analytical expression of the potential in the four regions.The analytic expression contains the coefficient to be determined,and uses the eigenfunction to expand the convergence condition to obtain the solution of the coefficient to be determined.The solution is substituted into the analytical expression of the potential at each region to obtain the potential distribution of the four regions.Based on this,the Bisection method and the Iterative method are used to solve the zero point beyond the equation to obtain the threshold voltage value.The thesis also discusses the threshold voltage and DIBL(DIBL)of high-k +SiO2 gate FDSOI MOSFET.By comparing different physical parameters,the model calculation results are compared with Silvaco simulation.The comparison shows that the error of model calculation is very high This verifies the accuracy of the model calculation.The thesis also analyzes the formation mechanism of FIBL effect,proposes its boundary conditions and describes the FIBL effect mechanism more accurately.It is found that the dielectric constant of high-k dielectric leads to the degradation of the device by changing the dielectric constant and gate physical thickness,which has little to do with the physical layer thickness of the gate.The high k+ SiO2 gate can also overcome the FIBL effect effects on device performance. |
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