Design Of 10Gbps CMOS High Sensitive Transimpedance Amplifier

Highly integrated communication systems are required to fulfill the growing demand for higher data rates in telecommunication networks.The optical fiber links are the best candidates to deal with these large volumes of data since it provides superior performances compared toconventional electrical links in terms of bandwidth,channel loss,electromagnetic interference,reflection,and crosstalk.The TIA?Transimpedance Amplifier?is the most critical building block at the optical receiver side in an optical communication system affecting the system speed and noise-sensitivity.Costly III-V materials such as GaAs and InP have been exploited to realize high-speed and low-noise TIAs.However,silicon deep-submicron CMOS technologies become more attractive due to their high integration density and low chip costs,and it has become one of design challenges because of it's serious parasitic capacitance,low transconductance and poor noise performance.The main bandwidth limitation of the TIA is at the input node due to the large photodiodecapacitance.Inductive peaking is effective both in bandwidth enhancement and noise reduction.However,the inductor occupies a large chip area making it unsuitable for cheap optical receivers.Also the substrate coupling increases through the inductors,resulting in higher crosstalk.The large group delay fluctuation is also an issue.The bandwidth of TIAs can be increased by using capacitive degeneration which adds an extra zero that compensates the dominant pole.This goes on the expense of lower DC gain.Firstly,this paper introduces the research status of 10Gbps TIA based on CMOS technology at home and abroad,and points out that it is difficult to balance the high speed,high sensitivity,chip area and power consumption.The author hopes to change this phenomenon from the circuit structure,uses improved RGC structure at the input stage,the circuit still has high bandwidth without the use of inductance,and has a good noise performance.Based on the TSMC 65nm CMOS technology,this paper presents a design of a transimpedance amplifier with high sensitivity to 10Gbps,including input stage circuit,transimpedance amplifier,single turn double and 50 matching circuit and peripheral DC power supply circuit.With a low supply voltage of 1.2V,the power consumption is only11.7mW.When the detector capacitance is 250fF,the transimpedance gain is 66dBWand the bandwidth is 30KHz-8.5GHz.The average equivalent input current spectral density is about 15pA????0¹0GHz?,integral input noise current is 1.2uA?integral area is 1KHz-10GHz?.When the Responsivity is 0.9A/W,ER=10dB,BER=10^-12,PRBS=2³¹-1,the sensitivity reached-20.1d Bm.The whole circuit is designed without inductance,the layout area of chip is only 115um×120um.