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The Structure Design And Simulation Research Of 4H-SiC Power UMOSFET Device

Posted on:2016-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:K TianFull Text:PDF
GTID:2348330542976150Subject:Electronic and communication engineering
Abstract/Summary:PDF Full Text Request
With the development of the electric and electronic power system,the performances of semiconductor electronic devices at high temperature and high voltage,high frequency and intense radiation environment are also put forward higher requirements.Silicon carbide materials have become the focus of power semiconductor devices research because of its wide bandgap,high heat conductivity,high breakdown voltage,high electron saturation velocity and strong radiation resistance.This paper selected 4H-SiC as UMOSFET device material and proposed two kinds of new structure to solve the large on-resistance of traditional p+ shielding SiC UMOSFET.Simulation and research were implemented as following:1.We proposed an improved structure to solve the shortcomings of p+ shielding SiC UMOSFET.This paper proposed an optimized p+ shielding SiC UMOSFET device.There was a high concentration n type wrapping region around the p+ shielding region in the optimized p+ shielding SiC UMOSFET The added region reduced depletion region formed by p+ shielding region and transmitted electrons downward.It's the key part of the improved device.In this paper,the concentration and the width of added region were simulated and discussed to analyze the effect of parameter changes on the device performance.At the same time,we analyzed the influence on frequency characteristic of device by gate charge simulation.This paper proposed a brief device manufacturing process to show the realizability of device,too.2.Another improved structure was proposed to reduce the large on-resistance of p+ shielding SiC UMOSFET.This structure reduced the resistance of depletion region formed by p+ shielding region to the electrons by using step trench.The gate charge increased because of the presence of step trench.So we introduced a p-n junction to reduce the gate charge.The gate coupling with the source region and drain region reduced due to the presence of the depletion layer between the n+ region and p region in the trench.In this paper we discussed the influence of step with and depth on on-resistance breakdown voltage and electric field oxide because we pay more attention on reducing on-resistance.The p-n junction in trench was not the research priority and didn't discuss it in this paper.
Keywords/Search Tags:4H-SiC, UMOSFET, on-resistance, breakdown voltage, gate-charge, FoM
PDF Full Text Request
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