Design Study And Optimization Of Cell For 100V UMOS Device

With the increasing support of the country to the integrated circuit industry,the demand for domestic semiconductor products is also increasing.Power device is a significant part of the semiconductor industry.It does not require particularly sophisticated process,and is an important breakthrough for catching up with the similar foreign products.Power MOSFET is one of the main products of power device,whose technical barriers is relatively low.Therefore,focusing on improving the performance of power MOSFET is conducive to accelerating the realization of the goal of localized substitution and improving the competitiveness of domestic power MOSFET products in the world market.At the same time,the rise of new energy vehicles such as electric vehicles,the construction of 5G base stations,the deployment of smart grids and other national new infrastructure construction projects require a considerable number of the power MOSFET with superior performance.It is foreseeable that the power MOSFET will have a very broad market and extremely high research value in the future.In this thesis,a 100V UMOS device is designed,studied and optimized.The conventional UMOS device structure is taken as the design object.In terms of the simulation,the Sentaurus TCAD software is used for simulation according to the given process and the images of device structure after the completion of the key process are displayed through the SPROCESS tool.Furthermore,the static electrical characteristic curves of the device are obtained through the SDEVICE tool,and extract the corresponding static electrical parameters from them.In terms of the layout,the layout of the 100V UMOS device is drawn on the basis of the position of the masks and the fab process rules.At last,comparing it with the device which has the similar performance in the market to prove that the designed device has better performance.In addition,the simulation results show that the on-resistance flatness changes regularly with the changes of the gate oxide thickness and P-well implantation dose.Thereupon,the main factors affecting the on-resistance flatness are studied through theoretical analysis,and the influence trend of these factors is verified through simulation.Studies have found that gate oxide thickness,electron mobility in the channel,and channel length are important factors affecting the on-resistance flatness.The smaller the gate oxide thickness and the P-well implantation dose,the better the on-resistance flatness.Finally,a method which called extra phosphorus implantation is proposed to optimize the100V UMOS device from the process.Extra phosphorus implantation can be performed after field oxide etching or before N~+implantation without adding new masks.Compare the characteristics of the two ways to provide guidance for future work.The simulation results indicate that the first way will reduce the threshold voltage,breakdown voltage and on-resistance,the larger the implantation dose,the more they decrease.At this point,the magnitude of the implantation energy hardly affects the device's static electrical parameters.The second way will lower the threshold voltage,and the larger the implantation dose and the implantation energy,the more the threshold voltage decreases while the breakdown voltage and on-resistance are hardly affected.