New Structure Design And Characteristics Research Of SiC UMOSFET

Silicon carbide?SiC?devices are used in the power electronics field of military equipment such as photovoltaic power generation,train traction equipment,ships,aerospace,etc.due to their advantages of high voltage,high frequency,high temperature resistance,radiation resistance,high reliability and high power.And greatly promote the development of high efficiency,low energy consumption and lightweight miniaturization of power equipment.Trench-type SiC MOSFETs,also known as SiC UMOSFETs,have the advantages of high cell density and no JFET regions,further reducing system losses.In this thesis,a new structure is proposed around the scientific issues of gate oxide reliability and bipolar degradation of SiC UMOSEFET.Based on the Sentaurus TCAD simulation platform,the new structural cell parameters of the deep P⁺SiC UMOSFET with a breakdown voltage of 1200V were designed for the reliability of the gate oxide layer.The key parameters,including CSL layer concentration,the distance W_N+between the deep P⁺source region and the P⁺shield layer,and the Pbase region concentration were optimized considering the trade-off of the breakdown voltage,threshold voltage and on-resistance.The breakdown voltage of SiC UMOSFET was 1783V,the specific on-resistance is 2.04m??cm²,and the maximum electric field at the bottom of the device is less than 3MV/cm.on the condition of that the doping concentration and thickness of drift layer,CSL layer concentration,the distance W_N+between the deep P⁺source region were 7.5×10¹⁵cm^-3/12?m,2×10¹⁶cm^-3,0.9?m respectively and the Pbase region concentration was 2×10¹⁷cm^-3.Based on the Sentaurus TCAD simulation platform,for the bipolar degradation problem and the third conduction voltage drop optimization problem of SiC UMOSEFET,this thesis optimizes the cell parameters of SiC MOSFET structure with integrated low-on-voltage drop diode with 1200V breakdown voltage.The tradeoff is to consider the breakdown voltage and the third quadrant conduction voltage drop,optimize the drift region concentration,the distance between the Pbase1 and Pbase2 regions W_N2,the bottom of the N₂ region to the bottom of the Pbase1 region and the Pbase2 region L_ch,and the concentration of the Pbase1 region and the Pbase2 region B.And device breakdown voltage was 1603V and third The quadrant pressure drop was 1.41V.On the condition of that the drift region concentration and thickness,W_N2,L_ch were 7.5×10¹⁵cm^-3/12?m,0.8?m,1.3?m respectively and the concentration of the Pbase1 region and the Pbase2region B was 4×10¹⁸cm^-3.In this thesis,the terminal structure of the SiC UMOSFET field limiting ring is compared,and finally the slowly varying pitch terminal structure is selected.At the same time,the process flow of the new structure is designed,and different layouts are drawn according to the different process flow.This thesis mainly proposes a solution and design idea for the gate oxide reliability and bipolar degradation of 1200V SiC UMOSFET devices,and provides the basis for the theoretical research of the SiC UMOSFET device.