Structure Design And Numerical Simulation Of Power 4H-SiC UMOSFET

The third generation semiconductor material silicon carbide（SiC）is widely used in high temperature,high voltage and high frequency environment due to its superior physical properties including wide band gap,high critical breakdown electric field,high saturation electron drift speed and high thermal conductivity.4H-SiC UMOSFET is widely used in power electronic system equipment for its low on-resistance and high current density.However,due to the concentrated effect of the electric field at the corner of the trench gate,the gate oxygen breakdown is easy to occur in the 4H-SiC UMOSFET device,which makes the performance of the device deteriorates seriously.A p⁺-SiC shielded 4H-SiC UMOSFET structure effectively protects the trench gate oxide layer,improving the electric field concentration effect at the corner of the trench gate and the breakdown voltage of the device.At the same time,this structure also sharply increases the specific on-resistance of the device and the conduction loss of the device.In this paper,based on the shortcomings of the large on-resistance of p⁺-SiC shielded 4H-SiC UMOSFET,we study three kinds of new 4H-SiC UMOSFET structures which can reduce the on-resistance of devices.the performance of these three structures are simulated and discussed.1.The 4H-SiC UMOSFET structure with a p/n alternating buffer layer is studied.The new structure is characterized by the existence of a p-and n-region alternately arranged buffer layer in in the drift region.Under the off-state,the p/n alternating buffer layer effectively protects the gate oxide layer and reduces the electric field of the gate oxide layer.Under on-state,the p/n alternating buffer layer is far away from the p-body region,which effectively reduces the influence of JFET resistance and the specific on-resistance of the new structure.At the same time,a pn junction is introduced in the gate trench of the new structure,which reduces the gate-drain capacitance of the device.This makes the gate charge characteristics of the device do not deteriorate seriously.In addition,the key parameters of the p/n alternating buffer layer on the electrical characteristics of the device are also simulated and discussed.This key parameters include the width（W）of p region,the doping concentration（NAp）of p region and the doping concentration(N_Dn)of n region.2.The 4H-SiC UMOSFET structure with a p type prominent shielded region is studied.The structure has two features:（1）the p type shielded region is located below the p-body region,which can effectively protect the gate oxide layer.Meanwhile,the region does not obstruct the current flowing down vertically,and effectively reduces the specific on-resistance of the device.（2）there is also a p⁺-polySi region on the structural surface of the device.The polySi/n-SiC heterojunction diode formed in the p⁺-polySi region and drift region has Schottky characteristics and low forward conduction pressure drop,which effectively improves the device's reverse recovery characteristics.In addition,the key parameters of the p type prominent shielded region on the electrical characteristics of the device are also simulated and discussed.This key parameters include the width（W_s）and the length（L_s）of p type shielded region.3.The 4H-SiC UMOSFET structure with a p⁺-polySi/SiC shielded region is studied.Due to low built-in potential in the polySi/SiC heterojunction,the structure shows low specific on-resistance,and the breakdown voltage of the device is not degraded.The p⁺-polySi/SiC shielded region is also located at the bottom of the trench gate,which also effectively protects the gate oxide layer.At the same time,the p⁺-polySi/n-SiC heterojunction diode is formed in the device,which improves the device's reverse recovery characteristics.In addition,we simulated and studied the influence of the ratio of the thickness(L_polySi)of the polySi region and the thickness(L_SiC)of the SiC region on the electrical characteristics of the device.