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Design And Performance Analysis Of On - Chip Network Adaptive Routing Algorithm

Posted on:2016-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:Y Q YueFull Text:PDF
GTID:2208330464463530Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of the semiconductor manufacturing technology, the bus structure of SoCrestricts its own development severely, the network transfer rate cann’t meet the needs of users. In order to solve the problems of the bus, the paper proposes the idea of ’ NoC ’, the research of NoC has drawn more attention. The main research direction of network are topology, routing algorithm, flow control, deadlock- free, fault tolerance and performance analysis. This paper studies the direction of the adaptive routing algorithm, the adaptive routing algorithm can not only consider network continuity, but also consider the needs of the network, in order to achieve optimal network performance.We analyze the current development situation of Network on Chip at home and abroad, we analyze the significance of this study, various types of NoC routing algorithm and their advantages and disadvantages. On this basis, this paper proposes two adaptive routing algorithm that optimize network performance, to meet the needs of network users, according to the low- latency, low power consumption, no deadlock, the principle of balance between network performance without congestion.Under 2D Mesh structure, for one single path and congestion problems of XY routing algorithm, this paper presents a virtual channel based adaptive routing algorithm. This routing algorithm analyzes traffic status, select a suitable routing path for data transmission according to the network of fitness at first. Each routing node is added congestion control mechanisms for avoiding network congestion and improve network throughput. It is compared with the XY routing algorithm, the algorithm has greatly improved throughput, transmission delay and power consumption, in terms of performance.When it transfer data packets between the source node and the destination node farther apart under the network of on-chip 2D Mesh structure, latency and power consumption is relatively high and is likely to appear partial path congestion. This paper proposes an alternative routing algorithm and a new network topology Mesh- Tree. And this paper proposes a new routing algorithm, it analyzes the advantages and disadvantages of this routing algorithm. In the first aspect of the design of the network topology network structure is divided into several regions, and this adds a routing node on the upper area, this node as the data packets between the source/destination node transmission intermediary. This routing algorithm reduces the network latency and power consumption, reduce network congestion phenomenon.Two routing algorithms are proposed to sacrifice certain aspects of network p erformance in this paper, thereby they enhance the performance of the network in other areas: the scope of the first VARA routing algorithms of 2D Mesh structure improve the throughput, delay and power consumption performance; the second from the topology of the routing algorithm can change the network performance and increase network paths, but it is bad to expand the routing algorithm, can only apply to a specific route structure. So NoC design is critical to select the appropriate routing algorithm, whic h is not only related to the user’s needs, but also with the performance of the network related.
Keywords/Search Tags:Network on Chip, Routing Algorithm, Congestion, Routing, Virtual Channel
PDF Full Text Request
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