Design And Optimization Of Data-path In Coarse-grained Reconfigurable System For Communication Applications

With the rapid development of microelectronics,computer and other technologies,communication has become an indispensable part of the future information network.With both flexibility and efficiency,coarse-grained reconfigurable architecture(CGRA)is suitable for the implement of communication baseband signal processing.In order to meet the high performance requirements of the communication baseband signal processing,the computation resources in the reconfigurable system are multiplied.However,the area of on-chip memory and the access delay are increased correspondingly.If the data bandwidth is not enough,the computation parallelism and energy efficiency in reconfigurable system cannot be improved.Therefore,the design of data flow management strategy with low hardware overhead is very significant to improve the performance of reconfigurable system.In this thesis,the following innovations are done to improve the efficiency of data access.Firstly,the process of communication baseband signal processing in MIMO-OFDM system is analyzed.The kernel algorithms of communication baseband signal processing are extracted and the characteristics of data access of kernel algorithms are summarized as parallelism,locality and diversity of access patterns.Secondly,focusing on the problems of serious data access conflicts and inefficient access to memory in reconfigurable system,this thesis designs the parallel shared memory structure and multi-mode memory for optimization.Third,based on the optimized shared memory structure,this thesis proposes a dynamic data reconfiguration strategy based on data lifetime to dynamically allocate data to the on-chip shared memory structure,and designs a reconfigurable address generation unit to generate different address sequences and to dynamically adjust the mode of shared memory.As a result,the data access performance of reconfigurable system is effectively improved.In order to verify the optimization effects of the proposed strategy,the RTL simulation of the data-path subsystem is implemented.The experimental results show that,based on SMIC 40nm technology,the system frequency of RASP-II is 500MHz and the area of data-path subsystem is 1.55mm2.The optimization strategy proposed in this thesis makes the access performance of the data-path subsystem improved by 69.60 times.And the bandwidth utilization is increased by an average of 42.47%.Compared with other static strategies,the dynamic data reconfiguration strategy achieves better access performance with lower hardware overhead and provides higher flexibility.