Research On Dynamic Reconfigurable Baseband Processing Architecture And Circuit Design Method Based On Multi-type Arithmetic Units

Communication systems have developed rapidly with the growth of semiconductor industry, leading to a proliferation of many air interface standards and new technologies, especially the concept of Soft Defined Radio (SDR) and Cognitive Radio (CR). As a result, baseband signal processing platforms which can adapt to meet multiple standards are of great interest. Moreover, the continued evolution and increased sophistication of communications technologies has led to the need for an increasing amount of signal processing capability. Therefore, the architectures used must be extremely efficient. Nowadays, many colledges and companies are seeking for a processing architecture providing both sufficient flexibility and computing capability. In this background, reconfigurable architectures attract great attentions, as they have been proposed as a compromise approach as they are flexible, scalable and can provide reasonable computing capability.According to the alalysis of many proposed reconfigurable processing architectures, we find that the heterogeneous reconfigurable architectures have becomed a trend in the application specific domains, for example, graphic processing, cryptography, baseband processing, etc. However, in the basic reconfigurable executing unit design of architecures, recent research lacks of analysis of operational features. Moreover, due to the asymmetric architecture, the design of configurable bits control mechanism and global interconnection is complex. Furthmore, the software tool chain and design methology is not mature.In this research, we first analyze some baseband signal processing algorithms in two kinds of wideband communication systems, the Orthogonal Frequency Division Multiplexing (OFDM) systems and Spread Spectrum systems. We study some most commonly used baseband proessing algorithms and summize some features on operation and operand types in Chapter 2.In Chapter 3, we propose a reconfigurable processing architecture based on heterogeneous executing units. Based on a set of heterogeneous reconfigurable execution units (RCEUs), the proposed reconfigurable baseband processing architecture achieves a large computing capability while, at the same time, providing flexibility. Four types of reconfigurable executing units are proposed for various arithmetic and logic operations arising in baseband processing. Each reconfigurable executing unit is composed of a scalable array of homogeneous processing elements which are designed to meet a range of computational demands. Therefore, this architecture can obtain a high throughput due to its inherent data-parallelism, high degree of regularity and computationally-intensive nature. A control mechanism composed of homogeneous Engine slices is proposed. The heterogeneous RCEUs and data memory are abstracted into functional units with three kinds of control bits. Using these control bits, the structure and data flows for each RCEU can be determined.Associated software tools are also proposed in this research in Chapter 4. According to the design idea of the whole architecture, first the software tool chain is introduced. Then, an automatic hardware generation tool, a library buiding tool, a binary generation tool, and a task allocation and VLIW generation tool are studies, providing the reconfigurability of the architecture both before and after synthesis. In addition, we introduce the design methology on the heterogeneous reconfigurable baseband processing architecture. In this way, it's easy to define a unique system according to the application requirements, and simply implement baseband algorithms on this architecture.Finally, we study two baseband standards and map them on the proposed heterogeneous reconfigurable baseband processing architecture in Chapter 5. These design cases show how to map a specific system or algorithm on the reconfigurable architecture and prove the effectiveness of the architecture in advance. The two baseband standards are the IEEE 802.11a/g (OFDM System) and IEEE 802.11b/g (Spread Spectrum System), which have been analyzed in Chapter 2. Besides, we mapped a specific algorithm, Transform Decomposition, a widely used FFT algorithm in OFDM base Cognitive Radio with a lot of zero inputs/outputs, on the reconfigurable architecture, showing that our architecture is also suitable for algorithms with operation features proposed in Chapter 2. We also analyze the configuration time when the running standard is switched, showing the dynamic reconfigurability of the proposed architecture.